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| this document contains detailed information on power considerations, dc/ac electrical characteristics, and ac timing speci?ations for the mpc866/859 family (refer to table 1 for a list of devices). the mpc866p is the superset device of the mpc866/859 family. this document describes pertinent electrical and physical characteristics of the mpc8245. for functional characteristics of the processor, refer to the mpc866 powerquicc family users manual (mpc866um/d). this document contains the following topics: topic page section 1, ?verview 1 section 2, ?eatures 2 section 3, ?aximum tolerated ratings 7 section 4, ?hermal characteristics 9 section 5, ?ower dissipation 10 section 6, ?c characteristics 10 section 7, ?hermal calculation and measurement 11 section 8, ?ower supply and power sequencing 14 section 9, ?ayout practices 15 section 10, ?us signal timing 15 section 11, ?eee 1149.1 electrical speci?ations 44 section 12, ?pm electrical characteristics 46 section 13, ?topia ac electrical speci?ations 70 section 14, ?ec electrical characteristics 72 section 15, ?echanical data and ordering information 75 section 16, ?ocument revision history 88 1 overview the mpc866/859 is a derivative of motorola s mpc860 powerquicc family of devices. it is a versatile single-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications and communications and networking systems. the mpc866/859/859dsl provides enhanced atm functionality over that of other atm-enabled members of the mpc860 family. advance information mpc866ec/d rev. 1.4, 8/2003 mpc866/859 hardware specifications f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2 mpc866/859 hardware speci?ations motorola features features table 1 shows the functionality supported by the members of the mpc866/859 family. 2 features the following list summarizes the key mpc866/859 features: embedded single-issue, 32-bit powerpc core (implementing the powerpc architecture) with thirty-two 32-bit general-purpose registers (gprs) the core performs branch prediction with conditional prefetch, without conditional execution 4- or 8-kbyte data cache and 4- or 16-kbyte instruction cache (see table 1) 16-kbyte instruction cache (mpc866p and MPC859p) is four-way, set-associative with 256 sets; 4-kbyte instruction cache (mpc866t, MPC859t, and MPC859dsl) is two-way, set-associative with 128 sets. 8-kbyte data cache (mpc866p and MPC859p) is two-way, set-associative with 256 sets; 4-kbyte data cache(mpc866t, MPC859t, and MPC859dsl) is two-way, set-associative with 128 sets. cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache blocks caches are physically addressed, implement a least recently used (lru) replacement algorithm, and are lockable on a cache block basis. mmus with 32-entry tlb, fully associative instruction and data tlbs mmus support multiple page sizes of 4, 16, and 512 kbytes, and 8 mbytes; 16 virtual address spaces and 16 protection groups. advanced on-chip-emulation debug mode the mpc866/859 provides enhanced atm functionality over that of the mpc860sar. the mpc866/859 adds major new features available in 'enhanced sar' (esar) mode, including the following: improved operation, administration, and maintenance (oam) support oam performance monitoring (pm) support table 1. mpc866 family functionality part cache ethernet scc smc instruction data 10t 10/100 mpc866p 16 kbytes 8 kbytes up to 4 1 4 2 mpc866t 4 kbytes 4 kbytes up to 4 1 4 2 MPC859p 16 kbytes 8 kbytes 1112 MPC859t 4 kbytes 4 kbytes 1112 MPC859dsl 4 kbytes 4 kbytes 1 1 1 1 1 on the MPC859dsl, the scc (scc1) is for ethernet only. also, the MPC859dsl does not support the time slot assigner (tsa). 1 2 2 on the MPC859dsl, the smc (smc1) is for uart only. mpc852t 3 3 for more details on the mpc852t, please refer to the mpc852t hardware speci?ations. 4 kbytes 4 kbytes 2121 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 3 features multiple apc priority levels available to support a range of traf? pace requirements atm port-to-port switching capability without the need for ram-based microcode simultaneous mii (10/100base-t) and utopia (half-duplex) capability optional statistical cell counters per phy utopia level 2 compliant interface with added fifo buffering to reduce the total cell transmission time. (the earlier utopia level 1 speci?ation is also supported.) multi-phy support on the mpc866, MPC859p, and MPC859t four phy support on the mpc866/859 parameter ram for both spi and i 2 c can be relocated without ram-based microcode supports full-duplex utopia both master (atm side) and slave (phy side) operation using a 'split' bus aal2/vbr functionality is rom-resident. up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits) thirty-two address lines memory controller (eight banks) contains complete dynamic ram (dram) controller each bank can be a chip select or ras to support a dram bank up to 30 wait states programmable per memory bank glueless interface to page mode/edo/sdram, sram, eproms, ?sh eproms, and other memory devices. dram controller programmable to support most size and speed memory interfaces four cas lines, four we lines, and one oe line boot chip-select available at reset (options for 8-, 16-, or 32-bit memory) variable block sizes (32 kbytes?56 mbytes) selectable write protection on-chip bus arbitration logic general-purpose timers four 16-bit timers cascadable to be two 32-bit timers gate mode can enable/disable counting interrupt can be masked on reference match and event capture fast ethernet controller (fec) simultaneous mii (10/100base-t) and utopia operation when using the utopia multiplexed bus system integration unit (siu) bus monitor software watchdog periodic interrupt timer (pit) low-power stop mode clock synthesizer decrementer and time base from the powerpc architecture reset controller f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4 mpc866/859 hardware speci?ations motorola features features ieee 1149.1 test access port (jtag) interrupts seven external interrupt request (irq) lines twelve port pins with interrupt capability the mpc866p and mpc866t have 23 internal interrupt sources; the MPC859p, MPC859t, and MPC859dsl have 20 internal interrupt sources. programmable priority between sccs (mpc866p and mpc866t) programmable highest priority request communications processor module (cpm) risc controller communication-speci? commands (for example, graceful stop transmit , enter hunt mode , and restart transmit ) supports continuous mode transmission and reception on all serial channels up to 8-kbytes of dual-port ram mpc866p and mpc866t have 16 serial dma (sdma) channels; MPC859p, MPC859t, and MPC859dsl have 10 serial dma (sdma) channels. three parallel i/o registers with open-drain capability four baud rate generators independent (can be connected to any scc or smc) allow changes during operation autobaud support option mpc866p and mpc866t have four sccs (serial communication controller); MPC859p, MPC859t, and MPC859dsl have one scc; and scc1 on MPC859dsl supports ethernet only. serial atm capability on all sccs optional utopia port on scc4 ethernet/ieee 802.3 optional on scc1?, supporting full 10-mbps operation hdlc/sdlc hdlc bus (implements an hdlc-based local area network (lan)) asynchronous hdlc to support ppp (point-to-point protocol) appletalk universal asynchronous receiver transmitter (uart) synchronous uart serial infrared (irda) binary synchronous communication (bisync) totally transparent (bit streams) totally transparent (frame based with optional cyclic redundancy check (crc) two smcs (serial management channels) (MPC859dsl has one smc (smc1) for uart.) uart transparent general circuit interface (gci) controller can be connected to the time-division multiplexed (tdm) channels f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 5 features one serial peripheral interface (spi) supports master and slave modes supports multiple-master operation on the same bus one inter-integrated circuit (i 2 c) port supports master and slave modes multiple-master environment support time slot assigner (tsa) (MPC859dsl does not have tsa.) allows sccs and smcs to run in multiplexed and/or non-multiplexed operation supports t1, cept, pcm highway, isdn basic rate, isdn primary rate, user-de?ed 1- or 8-bit resolution allows independent transmit and receive routing, frame synchronization, and clocking allows dynamic changes on mpc866p and mpc866t, can be internally connected to six serial channels (four sccs and two smcs); on MPC859p and MPC859t, can be connected to three serial channels (one scc and two smcs). parallel interface port (pip) centronics interface support supports fast connection between compatible ports on mpc866/859 or mc68360 pcmcia interface master (socket) interface, compliant with pci local bus speci?ation (rev 2.1) supports one or two pcmcia sockets whether esar functionality is enabled eight memory or i/o windows supported debug interface eight comparators: four operate on instruction address, two operate on data address, and two operate on data. supports conditions: = < > each watchpoint can generate a breakpoint internally normal high and normal low power modes to conserve power 1.8 v core and 3.3 v i/o operation with 5-v ttl compatibility; refer to table 6 for a listing of the 5-v tolerant pins. 357-pin plastic ball grid array (pbga) package operation up to 133 mhz the mpc866/859 is comprised of three modules that each use a 32-bit internal bus: mpc8xx core, system integration unit (siu), and communication processor module (cpm). the mpc866p block diagram is shown in figure 1 on page 6. the MPC859p/859t/859dsl block diagram is shown in figure 2 on page 7. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6 mpc866/859 hardware speci?ations motorola features features figure 1. mpc866p block diagram scc3 scc4 bus system interface unit (siu) embedded parallel i/o memory controller 4 timers interrupt controllers 8-kbyte dual-port ram 16 virtual serial and 2 independent dma channels system functions pcmcia/ata interface 16-kbyte instruction cache 32-entry itlb instruction mmu 8-kbyte data cache 32-entry dtlb data mmu instruction bus load/store bus unified 4 baud rate generators parallel interface port and utopia internal bus interface unit external bus interface unit timers 32-bit risc controller and program rom scc1 serial interface i 2 c spi smc2 smc1 scc2 time slot assigner mpc8xx processor core dmas fifos 10/100 mii base-t media access time slot assigner control fast ethernet controller f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 7 maximum tolerated ratings figure 2. MPC859p/859t/MPC859dsl block diagram 3 maximum tolerated ratings this section provides the maximum tolerated voltage and temperature ranges for the mpc866/859. table 2 shows the maximum tolerated ratings, and table 3 shows the operating temperatures. table 2. maximum tolerated ratings rating symbol value unit supply voltage 1 vddh ?0.3 to 4.0 v vddl ?0.3 to 2.0 v vddsyn ?0.3 to 2.0 v difference between vddl to vddsyn 100 mv bus system interface unit (siu) embedded parallel i/o memory controller 4 timers interrupt controllers 8-kbyte dual-port ram 10 virtual serial and 2 independent dma channels system functions pcmcia/ata interface 4-kbyte ? instruction cache 32-entry itlb instruction mmu 4-kbyte ? data cache 32-entry dtlb data mmu instruction bus load/store bus unified 4 baud rate generators parallel interface port and utopia internal bus interface unit external bus interface unit timers 32-bit risc controller and program rom scc1 serial interface i 2 c spi smc2* smc1 time slot assigner mpc8xx processor core dmas fifos 10/100 mii base-t media access time slot assigner* control fast ethernet controller * the MPC859dsl does not contain smc2 nor the time slot assigner, and provides eight sdma controllers. ? the MPC859p has a 16-kbyte instruction cache and a 8-kbyte data cache. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 8 mpc866/859 hardware speci?ations motorola maximum tolerated ratings maximum tolerated ratings table 3. operating temperatures this device contains circuitry protecting against damage due to high-static voltage or electrical ?lds; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either gnd or v dd ). input voltage 2 v in gnd ?0.3 to vddh v storage temperature range t stg ?5 to +150 ?c 1 the power supply of the device must start its ramp from 0.0 v. 2 functional operating conditions are provided with the dc electrical speci?ations in table 6. absolute maximum ratings are stress ratings only; functional operation at the maxima is not guaranteed. stress beyond those listed may affect device reliability or cause permanent damage to the device. see page 14. caution : all inputs that tolerate 5 v cannot be more than 2.5 v greater than vddh. this restriction applies to power-up and normal operation (that is, if the mpc866/859 is unpowered, a voltage greater than 2.5 v must not be applied to its inputs). rating symbol value unit temperature 1 (standard) 1 minimum temperatures are guaranteed as ambient temperature, t a . maximum temperatures are guaranteed as junction temperature, t j . t a(min) 0?c t j(max) 95 ?c temperature (extended) t a(min) ?0 ?c t j(max) 100 ?c table 2. maximum tolerated ratings (continued) rating symbol value unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 9 thermal characteristics 4 thermal characteristics table 4 shows the thermal characteristics for the mpc866/859. table 4. mpc866/859 thermal resistance data rating environment symbol value unit junction-to-ambient 1 1 junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air?w, power dissipation of other components on the board, and board thermal resistance. natural convection single-layer board (1s) r ja 2 2 per semi g38-87 and jedec jesd51-2 with the single-layer board horizontal. 37 ?/w four-layer board (2s2p) r jma 3 3 per jedec jesd51-6 with the board horizontal. 23 air?w (200 ft/min) single-layer board (1s) r jma 3 30 four-layer board (2s2p) r jma 3 19 junction-to-board 4 4 thermal resistance between the die and the printed-circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. r jb 13 junction-to-case 5 5 indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1) with the cold plate temperature used for the case temperature. for exposed pad packages where the pad would be expected to be soldered, junction-to-case thermal resistance is a simulated value from the junction to the exposed pad without contact resistance. r jc 6 junction-to-package top 6 6 thermal characterization parameter indicating the temperature difference between package top and junction temperature per jedec jesd51-2. natural convection jt 2 air?w (200 ft/min) jt 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 10 mpc866/859 hardware speci?ations motorola power dissipation power dissipation 5 power dissipation table 5 shows power dissipation information. the modes are 1:1, where cpu and bus speeds are equal, and 2:1 mode, where cpu frequency is twice the bus speed. 6 dc characteristics table 6 shows the dc electrical characteristics for the mpc866/859. table 5. power dissipation (p d ) die revision bus mode cpu frequency typical 1 1 typical power dissipation at vddl and vddsyn is at 1.8 v. and vddh is at 3.3 v. maximum 2 2 maximum power dissipation at vddl and vddsyn is at 1.9 v, and vddh is at 3.465 v. note values in table 5 represent vddl based power dissipation and do not include i/o power dissipation over vddh. i/o power dissipation varies widely by application due to buffer current, depending on external circuitry. the vddsyn power dissipation is negligible. unit 0 1:1 50 mhz 110 140 mw 66 mhz 150 180 mw 2:1 66 mhz 140 160 mw 80 mhz 170 200 mw 100 mhz 210 250 mw 133 mhz 260 320 mw table 6. dc electrical speci?ations characteristic symbol min max unit operating voltage vddl (core) 1.7 1.9 v vddh (i/o) 3.135 3.465 v vddsyn 1 1.7 1.9 v difference between vddl to vddsyn 100 mv input high voltage (all inputs except extal and extclk) 2 vih 2.0 3.465 v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 11 thermal calculation and measurement 7 thermal calculation and measurement for the following discussions, p d = (vddl x iddl) + pi/o, where pi/o is the power dissipation of the i/o drivers. the vddsyn power dissipation is negligible. input low voltage vil gnd 0.8 v extal, extclk input high voltage vihc 0.7*(vddh) vddh v input leakage current, vin = 5.5v (except tms, trst , dsck and dsdi pins) for 5 volts tolerant pins 2 i in 100 ? input leakage current, vin = vddh (except tms, trst , dsck, and dsdi) i in ?0 a input leakage current, vin = 0 v (except tms, trst , dsck and dsdi pins) i in ?0 a input capacitance 3 c in ?0pf output high voltage, ioh = ?2.0 ma, except xtal, and open drain pins voh 2.4 v output low voltage iol = 2.0 ma (clkout) iol = 3.2 ma 4 iol = 5.3 ma 5 iol = 7.0 ma (txd1/pa14, txd2/pa12) iol = 8.9 ma (ts , t a , tea , bi , bb , hreset , sreset ) vol 0.5 v 1 the difference between vddl and vddsyn can not be more than 100 m v. 2 the signals pa[0:15], pb[14:31], pc[4:15], pd[3:15], tdi, tdo, tck, trst _b, tms, mii_txen, mii_mdio are 5 v tolerant. 3 input capacitance is periodically sampled. 4 a(0:31), tsiz0/reg , tsiz1, d(0:31), dp(0:3)/irq (3:6), rd/wr , b urst , rsv /irq2 , ip_b(0:1)/iwp(0:1)/vfls(0:1), ip_b2/iois16_b/at2, ip_b3/iwp2/vf2, ip_b4/lwp0/vf0, ip_b5/lwp1/vf1, ip_b6/dsdi/at0, ip_b7/ptr/at3, rxd1 /pa15, rxd2/pa13, l1txdb/pa11, l1rxdb/pa10, l1txda/pa9, l1rxda/pa8, tin1/l1rclka/brgo1/clk1/pa7, brgclk1/t out1 /clk2/pa6, tin2/l1tclka/brgo2/clk3/pa5, t out2 /clk4/pa4, tin3/brgo3/clk5/pa3, brgclk2/l1rclkb/t out3 /clk6/pa2, tin4/brgo4/clk7/pa1, l1tclkb/t out4 /clk8/pa0, rejct1 /spisel /pb31, spiclk/pb30, spimosi/pb29, brgo4/spimiso/pb28, brgo1/i2csda/pb27, brgo2/i2cscl/pb26, smtxd1/pb25, smrxd1/pb24, smsyn1 /sd a ck1 /pb23, smsyn2 /sd a ck2 /pb22, smtxd2/l1clkob/pb21, smrxd2/l1clkoa/pb20, l1st1/r ts1 /pb19, l1st2/r ts2 /pb18, l1st3/l1rqb /pb17, l1st4/l1rqa /pb16, brgo3/pb15, rstr t1 /pb14, l1st1/r ts1 /dreq0 /pc15, l1st2/r ts2 /dreq1 /pc14, l1st3/l1rqb /pc13, l1st4/l1rqa /pc12, cts1 /pc11, tga te1 /cd1 /pc10, cts2 /pc9, tga te2 /cd2 /pc8, cts3 /sd a ck2 /l1tsyncb/pc7, cd3 /l1rsyncb/pc6, cts4 /sd a ck1 /l1tsynca/pc5, cd4 /l1rsynca/pc4, pd15/l1tsynca, pd14/l1rsynca, pd13/l1tsyncb, pd12/l1rsyncb, pd11/rxd3, pd10/txd3, pd9/rxd4, pd8/txd4, pd5/reject2, pd6/r ts4 , pd7/r ts3 , pd4/reject3, pd3, mii_mdc, mii_tx_er, mii_en, mii_mdio, mii_txd[0:3]. 5 bdip /gpl_b (5), br , bg , frz/irq6 , cs (0:5), cs (6)/ce (1)_b, cs (7)/ce (2)_b, we0 /bs _b0/iord , we1 /bs _b1/io wr , we2 /bs _b2/pcoe , we3 /bs _b3/pcwe , bs _a(0:3), gpl_a0 /gpl_b0 , oe /gpl_a1 /gpl_b1 , gpl_a (2:3)/gpl_b (2:3)/cs (2:3), upwaita/gpl_a4 , upwaitb/gpl_b4 , gpl_a5 , ale_a, ce 1_a, ce 2_a, ale_b/dsck/at1, op(0:1), op2/modck1/sts , op3/modck2/dsdo, baddr(28:30). table 6. dc electrical speci?ations (continued) characteristic symbol min max unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 12 mpc866/859 hardware speci?ations motorola thermal calculation and measurement thermal calculation and measurement 7.1 estimation with junction-to-ambient thermal resistance an estimation of the chip junction temperature, t j , in ? can be obtained from the equation: t j = t a +(r ja x p d ) where: t a = ambient temperature (?) r ja = package junction-to-ambient thermal resistance (?/w) p d = power dissipation in package the junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. however, the answer is only an estimate; test cases have demonstrated that errors of a factor of two (in the quantity t j -t a ) are possible. 7.2 estimation with junction-to-case thermal resistance historically, the thermal resistance has frequently been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: r ja = r jc + r ca where: r ja = junction-to-ambient thermal resistance (?/w) r jc = junction-to-case thermal resistance (?/w) r ca = case-to-ambient thermal resistance (?/w) r jc is device related and cannot be in?enced by the user. the user adjusts the thermal environment to affect the case-to-ambient thermal resistance, r ca . for instance, the user can change the air?w around the device, add a heat sink, change the mounting arrangement on the printed-circuit board, or change the thermal dissipation on the printed-circuit board surrounding the device. this thermal model is most useful for ceramic packages with heat sinks where some 90% of the heat ?ws through the case and the heat sink to the ambient environment. for most packages, a better model is required. 7.3 estimation with junction-to-board thermal resistance a simple package thermal model that has demonstrated reasonable accuracy (about 20%) is a two-resistor model consisting of a junction-to-board and a junction-to-case thermal resistance. the junction-to-case covers the situation where a heat sink is used or where a substantial amount of heat is dissipated from the top of the package. the junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed-circuit board. it has been observed that the thermal performance of most plastic packages and especially pbga packages is strongly dependent on the board temperature; see figure 3. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 13 thermal calculation and measurement figure 3. effect of board temperature rise on thermal behavior if the board temperature is known, an estimate of the junction temperature in the environment can be made using the following equation: t j = t b +(r jb x p d ) where: r jb = junction-to-board thermal resistance (?/w) t b = board temperature ? p d = power dissipation in package if the board temperature is known and the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. for this method to work, the board and board mounting must be similar to the test board used to determine the junction-to-board thermal resistance, namely a 2s2p (board with a power and a ground plane) and vias attaching the thermal balls to the ground plane. 7.4 estimation using simulation when the board temperature is not known, a thermal simulation of the application is needed. the simple two-resistor model can be used with the thermal simulation of the application [2], or a more accurate and complex model of the package can be used in the thermal simulation. 0 10 20 30 40 50 60 70 80 90 100 0 2040 6080 board temperture rise above ambient divided by package power junction temperature rise above ambient divided by package power f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 14 mpc866/859 hardware speci?ations motorola power supply and power sequencing power supply and power sequencing 7.5 experimental determination to determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter ( jt ) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: t j = t t +( jt x p d ) where: jt = thermal characterization parameter t t = thermocouple temperature on top of package p d = power dissipation in package the thermal characterization parameter is measured per jesd51-2 speci?ation published by jedec using a 40 gauge type t thermocouple epoxied to the top center of the package case. the thermocouple should be positioned so that the thermocouple junction rests on the package. a small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. the thermocouple wire is placed ?t against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. 7.6 references semiconductor equipment and materials international (415) 964-5111 805 east middle?ld rd. mountain view, ca 94043 mil-spec and eia/jesd (jedec) speci?ations 800-854-7179 or (available from global engineering documents) 303-397-7956 jedec speci?ations http://www.jedec.org 1. c.e. triplett and b. joiner, an experimental characterization of a 272 pbga within an automotive engine controller module,?proceedings of semitherm, san diego, 1998, pp. 47-54. 2. b. joiner and v. adams, ?easurement and simulation of junction to board thermal resistance and its application in thermal modeling,?proceedings of semitherm, san diego, 1999, pp. 212-220. 8 power supply and power sequencing this section provides design considerations for the mpc866/859 power supply. the mpc866/859 has a core voltage (vddl) and pll voltage (vddsyn) that operates at a lower voltage than the i/o voltage vddh. the i/o section of the mpc866/859 is supplied with 3.3 v across vddh and v ss (gnd). signals pa[0:15], pb[14:31], pc[4:15], pd[3:15], tdi, tdo, tck, trst_b, tms, mii_txen, and mii_mdio are 5-v tolerant. all inputs cannot be more than 2.5 v greater than vddh. in addition, 5-v tolerant pins cannot exceed 5.5 v and the remaining input pins cannot exceed 3.465 v. this restriction applies to power up/down and normal operation. one consequence of multiple power supplies is that when power is initially applied the voltage rails ramp up at different rates. the rates depend on the nature of the power supply, the type of load on each power supply, and the manner in which different voltages are derived. the following restrictions apply: vddl must not exceed vddh during power up and power down. vddl must not exceed 1.9 v and vddh must not exceed 3.465 v. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 15 layout practices these cautions are necessary for the long term reliability of the part. if they are violated, the electrostatic discharge (esd) protection diodes are forward-biased and excessive current can ?w through these diodes. if the system power supply design does not control the voltage sequencing, the circuit shown in figure 4 can be added to meet these requirements. the mur420 schottky diodes control the maximum potential difference between the external bus and core power supplies on powerup and the 1n5820 diodes regulate the maximum potential difference on powerdown. figure 4. example voltage sequencing circuit 9 layout practices each v dd pin on the mpc866/859 should be provided with a low-impedance path to the board s supply. furthermore, each gnd pin should be provided with a low-impedance path to ground. the power supply pins drive distinct groups of logic on chip. the v dd power supply should be bypassed to ground using at least four 0.1 ? bypass capacitors located as close as possible to the four sides of the package. each board designed should be characterized and additional appropriate decoupling capacitors should be used if required. the capacitor leads and associated printed-circuit traces connecting to chip v dd and gnd should be kept to less than 1/2?per capacitor lead. at a minimum, a four-layer board employing two inner layers as v dd and gnd planes should be used. all output pins on the mpc866/859 have fast rise and fall times. printed-circuit (pc) trace interconnection length should be minimized in order to minimize undershoot and re?ctions caused by these fast output switching times. this recommendation particularly applies to the address and data buses. maximum pc trace lengths of 6?are recommended. capacitance calculations should consider all device loads as well as parasitic capacitances due to the pc traces. attention to proper pcb layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the v dd and gnd circuits. pull up all unused inputs or signals that will be inputs during reset. special care should be taken to minimize the noise levels on the pll supply pins. for more information, please refer to section 14.4.3, clock synthesizer power (vddsyn, vsssyn, vsssyn1), in the mpc866 user s manual . 10 bus signal timing the maximum bus speed supported by the mpc866/859 is 66 mhz. higher-speed parts must be operated in half-speed bus mode (for example, an mpc866/859 used at 100 mhz must be con?ured for a 50-mhz bus). table 7 and table 8 show the frequency ranges for standard part frequencies. vddh vddl 1n5820 mur420 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 16 mpc866/859 hardware speci?ations motorola bus signal timing bus signal timing table 9 shows the timings for the mpc866/859 at 33, 40, 50, and 66 mhz bus operation. the timing for the mpc866/859 bus shown in this table assumes a 50-pf load for maximum delays and a 0-pf load for minimum delays. clkout assumes a 100-pf load maximum delay. table 7. frequency ranges for standard part frequencies (1:1 bus mode) part freq 50 mhz 66 mhz min max min max core 40 50 40 66.67 bus 40 50 40 66.67 table 8. frequency ranges for standard part frequencies (2:1 bus mode) part freq 50 mhz 66 mhz 100 mhz 133 mhz min max min max min max min max core 40 50 40 66.67 40 100 40 133.34 bus 20 25 20 33.33 20 50 20 66.67 table 9. bus operation timings num characteristic 33 mhz 40 mhz 50 mhz 66 mhz unit min max min max min max min max b1 bus period (clkout) see table 7 ns b1a extclk to clkout phase skew ?2 +2 ?2 +2 ?2 +2 ?2 +2 ns b1b clkout frequency jitter peak-to-peak 1 ???ns b1c frequency jitter on extclk 0.50 0.50 0.50 0.50 % b1d clkout phase jitter peak-to-peak for osclk 15 mhz 4???ns clkout phase jitter peak-to-peak for osclk < 15 mhz 5???ns b2 clkout pulse width low (min = 0.4 x b1, max = 0.6 x b1) 12.1 18.2 10.0 15.0 8.0 12.0 6.1 9.1 ns b3 clkout pulse width high (min = 0.4 x b1, max = 0.6 x b1) 12.1 18.2 10.0 15.0 8.0 12.0 6.1 9.1 ns b4 clkout rise time 4.00 4.00 4.00 4.00 ns b5 clkout fall time 4.00 4.00 4.00 4.00 ns b7 clkout to a(0:31), baddr(28:30), rd/wr , b urst , d(0:31), dp(0:3) output hold (min = 0.25 x b1) 7.60 6.30 5.00 3.80 ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 17 bus signal timing b7a clkout to tsiz(0:1), reg , rsv , at(0:3), bdip , ptr output hold (min = 0.25 x b1) 7.60 6.30 5.00 3.80 ns b7b clkout to br , bg , frz, vfls(0:1), vf(0:2), iwp(0:2), lwp(0:1), sts output hold (min = 0.25 x b1) 7.60 6.30 5.00 3.80 ns b8 clkout to a(0:31), baddr(28:30) rd/wr , b urst , d(0:31), dp(0:3), valid (max = 0.25 x b1 + 6.3) 13.80 12.50 11.30 10.00 ns b8a clkout to tsiz(0:1), reg , rsv , at(0:3), bdip , ptr valid (max = 0.25 x b1 + 6.3) 13.80 12.50 11.30 10.00 ns b8b clkout to br , bg , vfls(0:1), vf(0:2), iwp(0:2), frz, lwp(0:1), sts valid 4 (max = 0.25 x b1 + 6.3) 13.80 12.50 11.30 10.00 ns b9 clkout to a(0:31), baddr(28:30), rd/wr , b urst , d(0:31), dp(0:3), tsiz(0:1), reg , rsv , at(0:3), ptr high-z (max = 0.25 x b1 + 6.3) 7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns b11 clkout to ts , bb assertion (max = 0.25 x b1 + 6.0) 7.60 13.60 6.30 12.30 5.00 11.00 3.80 9.80 ns b11a clkout to t a , bi assertion (when driven by the memory controller or pcmcia interface) (max = 0.00 x b1 + 9.30 1 ) 2.50 9.30 2.50 9.30 2.50 9.30 2.50 9.80 ns b12 clkout to ts , bb negation (max = 0.25 x b1 + 4.8) 7.60 12.30 6.30 11.00 5.00 9.80 3.80 8.50 ns b12a clkout to t a , bi negation (when driven by the memory controller or pcmcia interface) (max = 0.00 x b1 + 9.00) 2.50 9.00 2.50 9.00 2.50 9.00 2.50 9.00 ns b13 clkout to ts , bb high-z (min = 0.25 x b1) 7.60 21.60 6.30 20.30 5.00 19.00 3.80 14.00 ns b13a clkout to t a , bi high-z (when driven by the memory controller or pcmcia interface) (min = 0.00 x b1 + 2.5) 2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns b14 clkout to tea assertion (max = 0.00 x b1 + 9.00) 2.50 9.00 2.50 9.00 2.50 9.00 2.50 9.00 ns b15 clkout to tea high-z (min = 0.00 x b1 + 2.50) 2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns b16 t a , bi valid to clkout (setup time) (min = 0.00 x b1 + 6.00) 6.00 6.00 6.00 6.00 ns table 9. bus operation timings (continued) num characteristic 33 mhz 40 mhz 50 mhz 66 mhz unit min max min max min max min max f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 18 mpc866/859 hardware speci?ations motorola bus signal timing bus signal timing b16a tea , kr , retr y , cr valid to clkout (setup time) (min = 0.00 x b1 + 4.5) 4.50 4.50 4.50 4.50 ns b16b bb , bg , br , valid to clkout (setup time) 2 (4 min = 0.00 x b1 + 0.00 ) 4.00 4.00 4.00 4.00 ns b17 clkout to t a , tea , bi , bb , bg , br valid (hold time) (min = 0.00 x b1 + 1.00 3 ) 1.00 1.00 1.00 2.00 ns b17a clkout to kr , retr y , cr valid (hold time) (min = 0.00 x b1 + 2.00) 2.00 2.00 2.00 2.00 ns b18 d(0:31), dp(0:3) valid to clkout rising edge (setup time) 4 (min = 0.00 x b1 + 6.00) 6.00 6.00 6.00 6.00 ns b19 clkout rising edge to d(0:31), dp(0:3) valid (hold time) 4 (min = 0.00 x b1 + 1.00 5 ) 1.00 1.00 1.00 2.00 ns b20 d(0:31), dp(0:3) valid to clkout falling edge (setup time) 6 (min = 0.00 x b1 + 4.00) 4.00 4.00 4.00 4.00 ns b21 clkout falling edge to d(0:31), dp(0:3) valid (hold time) 6 (min = 0.00 x b1 + 2.00) 2.00 2.00 2.00 2.00 ns b22 clkout rising edge to cs asserted gpcm acs = 00 (max = 0.25 x b1 + 6.3) 7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns b22a clkout falling edge to cs asserted gpcm acs = 10, trlx = 0 (max = 0.00 x b1 + 8.00) 8.00 8.00 8.00 8.00 ns b22b clkout falling edge to cs asserted gpcm acs = 11, trlx = 0, ebdf = 0 (max = 0.25 x b1 + 6.3) 7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns b22c clkout falling edge to cs asserted gpcm acs = 11, trlx = 0, ebdf = 1 (max = 0.375 x b1 + 6.6) 10.90 18.00 10.90 16.00 7.00 14.10 5.20 12.30 ns b23 clkout rising edge to cs negated gpcm read access, gpcm write access acs = 00, trlx = 0 & csnt = 0 (max = 0.00 x b1 + 8.00) 2.00 8.00 2.00 8.00 2.00 8.00 2.00 8.00 ns b24 a(0:31) and baddr(28:30) to cs asserted gpcm acs = 10, trlx = 0 (min = 0.25 x b1 - 2.00) 5.60 4.30 3.00 1.80 ns table 9. bus operation timings (continued) num characteristic 33 mhz 40 mhz 50 mhz 66 mhz unit min max min max min max min max f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 19 bus signal timing b24a a(0:31) and baddr(28:30) to cs asserted gpcm acs = 11, trlx = 0 (min = 0.50 x b1 - 2.00) 13.20 10.50 8.00 5.60 ns b25 clkout rising edge to oe , we (0:3) asserted (max = 0.00 x b1 + 9.00) 9.00 9.00 9.00 9.00 ns b26 clkout rising edge to oe negated (max = 0.00 x b1 + 9.00) 2.00 9.00 2.00 9.00 2.00 9.00 2.00 9.00 ns b27 a(0:31) and baddr(28:30) to cs asserted gpcm acs = 10, trlx = 1 (min = 1.25 x b1 - 2.00) 35.90 29.30 23.00 16.90 ns b27a a(0:31) and baddr(28:30) to cs asserted gpcm acs = 11, trlx = 1 (min = 1.50 x b1 - 2.00) 43.50 35.50 28.00 20.70 ns b28 clkout rising edge to we (0:3) negated gpcm write access csnt = 0 (max = 0.00 x b1 + 9.00) 9.00 9.00 9.00 9.00 ns b28a clkout falling edge to we (0:3) negated gpcm write access trlx = 0,1, csnt = 1, ebdf = 0 (max = 0.25 x b1 + 6.80) 7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns b28b clkout falling edge to cs negated gpcm write access trlx = 0,1, csnt = 1, acs = 10 or acs = 11, ebdf = 0 (max = 0.25 x b1 + 6.80) 14.30 13.00 11.80 10.50 ns b28c clkout falling edge to we (0:3) negated gpcm write access trlx = 0, csnt = 1 write access trlx = 0,1, csnt = 1, ebdf = 1 (max = 0.375 x b1 + 6.6) 10.90 18.00 10.90 18.00 7.00 14.30 5.20 12.30 ns b28d clkout falling edge to cs negated gpcm write access trlx = 0,1, csnt = 1, acs = 10, or acs = 11, ebdf = 1 (max = 0.375 x b1 + 6.6) 18.00 18.00 14.30 12.30 ns b29 we (0:3) negated to d(0:31), dp(0:3) high-z gpcm write access, csnt = 0, ebdf = 0 (min = 0.25 x b1 - 2.00) 5.60 4.30 3.00 1.80 ns b29a we (0:3) negated to d(0:31), dp(0:3) high-z gpcm write access, trlx = 0, csnt = 1, ebdf = 0 (min = 0.50 x b1 ?2.00) 13.20 10.50 8.00 5.60 ns b29b cs negated to d(0:31), dp(0:3), high z gpcm write access, acs = 00, trlx = 0,1 & csnt = 0 (min = 0.25 x b1?2.00) 5.60 4.30 3.00 1.80 ns table 9. bus operation timings (continued) num characteristic 33 mhz 40 mhz 50 mhz 66 mhz unit min max min max min max min max f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 20 mpc866/859 hardware speci?ations motorola bus signal timing bus signal timing b29c cs negated to d(0:31), dp(0:3) high-z gpcm write access, trlx = 0, csnt = 1, acs = 10, or acs = 11, ebdf = 0 (min = 0.50 x b1 ?2.00) 13.20 10.50 8.00 5.60 ns b29d we (0:3) negated to d(0:31), dp(0:3) high-z gpcm write access, trlx = 1, csnt = 1, ebdf = 0 (min = 1.50 x b1 ?2.00) 43.50 35.50 28.00 20.70 ns b29e cs negated to d(0:31), dp(0:3) high-z gpcm write access, trlx = 1, csnt = 1, acs = 10, or acs = 11, ebdf = 0 (min = 1.50 x b1 ?2.00) 43.50 35.50 28.00 20.70 ns b29f we (0:3) negated to d(0:31), dp(0:3) high z gpcm write access, trlx = 0, csnt = 1, ebdf = 1 (min = 0.375 x b1 ?6.30) 5.00 3.00 1.10 0.00 ns b29g cs negated to d(0:31), dp(0:3) high-z gpcm write access, trlx = 0, csnt = 1 acs = 10 or acs = 11, ebdf = 1 (min = 0.375 x b1 ?6.30) 5.00 3.00 1.10 0.00 ns b29h we (0:3) negated to d(0:31), dp(0:3) high z gpcm write access, trlx = 1, csnt = 1, ebdf = 1 (min = 0.375 x b1 ?3.30) 38.40 31.10 24.20 17.50 ns b29i cs negated to d(0:31), dp(0:3) high-z gpcm write access, trlx = 1, csnt = 1, acs = 10 or acs = 11, ebdf = 1 (min = 0.375 x b1 ?3.30) 38.40 31.10 24.20 17.50 ns b30 cs , we (0:3) negated to a(0:31), baddr(28:30) invalid gpcm write access 7 (min = 0.25 x b1 ?2.00) 5.60 4.30 3.00 1.80 ns b30a we (0:3) negated to a(0:31), baddr(28:30) invalid gpcm, write access, trlx = 0, csnt = 1, cs negated to a(0:31) invalid gpcm write access trlx = 0, csnt =1 acs = 10, or acs == 11, ebdf = 0 (min = 0.50 x b1 ?2.00) 13.20 10.50 8.00 5.60 ns b30b we (0:3) negated to a(0:31) invalid gpcm baddr(28:30) invalid gpcm write access, trlx = 1, csnt = 1. cs negated to a(0:31) invalid gpcm write access trlx = 1, csnt = 1, acs = 10, or acs == 11 ebdf = 0 (min = 1.50 x b1 ?2.00) 43.50 35.50 28.00 20.70 ns table 9. bus operation timings (continued) num characteristic 33 mhz 40 mhz 50 mhz 66 mhz unit min max min max min max min max f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 21 bus signal timing b30c we (0:3) negated to a(0:31), baddr(28:30) invalid gpcm write access, trlx = 0, csnt = 1. cs negated to a(0:31) invalid gpcm write access, trlx = 0, csnt = 1 acs = 10, acs == 11, ebdf = 1 (min = 0.375 x b1 ?3.00) 8.40 6.40 4.50 2.70 ns b30d we (0:3) negated to a(0:31), baddr(28:30) invalid gpcm write access trlx = 1, csnt =1, cs negated to a(0:31) invalid gpcm write access trlx = 1, csnt = 1, acs = 10 or 11, ebdf = 1 38.67 31.38 24.50 17.83 ns b31 clkout falling edge to cs valid, as requested by control bit cst4 in the corresponding word in the upm (max = 0.00 x b1 + 6.00) 1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns b31a clkout falling edge to cs valid, as requested by control bit cst1 in the corresponding word in the upm (max = 0.25 x b1 + 6.80) 7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns b31b clkout rising edge to cs valid, as requested by control bit cst2 in the corresponding word in the upm (max = 0.00 x b1 + 8.00) 1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns b31c clkout rising edge to cs valid, as requested by control bit cst3 in the corresponding word in the upm (max = 0.25 x b1 + 6.30) 7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns b31d clkout falling edge to cs valid, as requested by control bit cst1 in the corresponding word in the upm ebdf = 1 (max = 0.375 x b1 + 6.6) 13.30 18.00 11.30 16.00 9.40 14.10 7.60 12.30 ns b32 clkout falling edge to bs valid, as requested by control bit bst4 in the corresponding word in the upm (max = 0.00 x b1 + 6.00) 1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns b32a clkout falling edge to bs valid, as requested by control bit bst1 in the corresponding word in the upm, ebdf = 0 (max = 0.25 x b1 + 6.80) 7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns b32b clkout rising edge to bs valid, as requested by control bit bst2 in the corresponding word in the upm (max = 0.00 x b1 + 8.00) 1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns table 9. bus operation timings (continued) num characteristic 33 mhz 40 mhz 50 mhz 66 mhz unit min max min max min max min max f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 22 mpc866/859 hardware speci?ations motorola bus signal timing bus signal timing b32c clkout rising edge to bs valid, as requested by control bit bst3 in the corresponding word in the upm (max = 0.25 x b1 + 6.80) 7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns b32d clkout falling edge to bs valid- as requested by control bit bst1 in the corresponding word in the upm, ebdf = 1 (max = 0.375 x b1 + 6.60) 13.30 18.00 11.30 16.00 9.40 14.10 7.60 12.30 ns b33 clkout falling edge to gpl valid, as requested by control bit gxt4 in the corresponding word in the upm (max = 0.00 x b1 + 6.00) 1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns b33a clkout rising edge to gpl valid, as requested by control bit gxt3 in the corresponding word in the upm (max = 0.25 x b1 + 6.80) 7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns b34 a(0:31), baddr(28:30), and d(0:31) to cs valid, as requested by control bit cst4 in the corresponding word in the upm (min = 0.25 x b1 - 2.00) 5.60 4.30 3.00 1.80 ns b34a a(0:31), baddr(28:30), and d(0:31) to cs valid, as requested by control bit cst1 in the corresponding word in the upm (min = 0.50 x b1 ?2.00) 13.20 10.50 8.00 5.60 ns b34b a(0:31), baddr(28:30), and d(0:31) to cs valid, as requested by cst2 in the corresponding word in upm (min = 0.75 x b1 ?2.00) 20.70 16.70 13.00 9.40 ns b35 a(0:31), baddr(28:30) to cs valid, as requested by control bit bst4 in the corresponding word in the upm (min = 0.25 x b1 ?2.00) 5.60 4.30 3.00 1.80 ns b35a a(0:31), baddr(28:30), and d(0:31) to bs valid, as requested by bst1 in the corresponding word in the upm (min = 0.50 x b1 ?2.00) 13.20 10.50 8.00 5.60 ns b35b a(0:31), baddr(28:30), and d(0:31) to bs valid, as requested by control bit bst2 in the corresponding word in the upm (min = 0.75 x b1 ?2.00) 20.70 16.70 13.00 9.40 ns b36 a(0:31), baddr(28:30), and d(0:31) to gpl valid as requested by control bit gxt4 in the corresponding word in the upm (min = 0.25 x b1 ?2.00) 5.60 4.30 3.00 1.80 ns table 9. bus operation timings (continued) num characteristic 33 mhz 40 mhz 50 mhz 66 mhz unit min max min max min max min max f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 23 bus signal timing b37 upwait valid to clkout falling edge 8 (min = 0.00 x b1 + 6.00) 6.00 6.00 6.00 6.00 ns b38 clkout falling edge to upwait valid 8 (min = 0.00 x b1 + 1.00) 1.00 1.00 1.00 1.00 ns b39 as valid to clkout rising edge 9 (min = 0.00 x b1 + 7.00) 7.00 7.00 7.00 7.00 ns b40 a(0:31), tsiz(0:1), rd/wr , b urst , valid to clkout rising edge (min = 0.00 x b1 + 7.00) 7.00 7.00 7.00 7.00 ns b41 ts valid to clkout rising edge (setup time) (min = 0.00 x b1 + 7.00) 7.00 7.00 7.00 7.00 ns b42 clkout rising edge to ts valid (hold time) (min = 0.00 x b1 + 2.00) 2.00 2.00 2.00 2.00 ns b43 as negation to memory controller signals negation (max = tbd) tbd tbd tbd tbd ns 1 for part speeds above 50 mhz, use 9.80 ns for b11a. 2 the timing required for br input is relevant when the mpc866/859 is selected to work with the internal bus arbiter. the timing for bg input is relevant when the mpc866/859 is selected to work with the external bus arbiter. 3 for part speeds above 50 mhz, use 2 ns for b17. 4 the d(0:31) and dp(0:3) input timings b18 and b19 refer to the rising edge of clkout, in which the t a input signal is asserted. 5 for part speeds above 50 mhz, use 2 ns for b19. 6 the d(0:31) and dp(0:3) input timings b20 and b21 refer to the falling edge of clkout. this timing is valid only for read accesses controlled by chip-selects under control of the upm in the memory controller, for data beats, where dlt3 = 1 in the upm ram words. (this is only the case where data is latched on the falling edge of clkout.) 7 the timing b30 refers to cs when acs = 00 and to we (0:3) when csnt = 0. 8 the signal upwait is considered asynchronous to clkout and synchronized internally. the timings speci?d in b37 and b38 are speci?d to enable the freeze of the upm output signals as described in figure 20. 9 the as signal is considered asynchronous to clkout. the timing b39 is speci?d in order to allow the behavior speci?d in figure 23. table 9. bus operation timings (continued) num characteristic 33 mhz 40 mhz 50 mhz 66 mhz unit min max min max min max min max f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 24 mpc866/859 hardware speci?ations motorola bus signal timing bus signal timing figure 5 shows the control timing diagram. figure 5. control timing figure 6 shows the timing for the external clock. figure 6. external clock timing clkout outputs a b 2.0 v 0.8 v 0.8 v 2.0 v 2.0 v 0.8 v 2.0 v 0.8 v outputs 2.0 v 0.8 v 2.0 v 0.8 v b a inputs 2.0 v 0.8 v 2.0 v 0.8 v d c inputs 2.0 v 0.8 v 2.0 v 0.8 v c d a maximum output delay specification b minimum output hold time c minimum input setup time specification d minimum input hold time specification clkout b1 b5 b3 b4 b1 b2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 25 bus signal timing figure 7 shows the timing for the synchronous output signals. figure 7. synchronous output signals timing figure 8 shows the timing for the synchronous active pull-up and open-drain output signals. figure 8. synchronous active pull-up resistor and open-drain output signals timing clkout output signals output signals output signals b8 b7 b9 b8a b9 b7a b8b b7b clkout ts , bb t a , bi tea b13 b12 b11 b11a b12a b13a b15 b14 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 26 mpc866/859 hardware speci?ations motorola bus signal timing bus signal timing figure 9 shows the timing for the synchronous input signals. figure 9. synchronous input signals timing figure 10 shows normal case timing for input data. it also applies to normal read accesses under the control of the upm in the memory controller. figure 10. input data timing in normal case clkout t a , bi tea , kr , retr y , cr bb , bg , br b16 b17 b16a b17a b16b b17 clkout t a d[0:31], dp[0:3] b16 b17 b19 b18 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 27 bus signal timing figure 11 shows the timing for the input data controlled by the upm for data beats where dlt3 = 1 in the upm ram words. (this is only the case where data is latched on the falling edge of clkout.) figure 11. input data timing when controlled by upm in the memory controller and dlt3 = 1 figure 12 through figure 15 show the timing for the external bus read controlled by various gpcm factors. figure 12. external bus read timing (gpcm controlled?cs = 00) clkout t a d[0:31], dp[0:3] b20 b21 clkout a[0:31] cs x oe we [0:3] ts d[0:31], dp[0:3] b11 b12 b23 b8 b22 b26 b19 b18 b25 b28 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 28 mpc866/859 hardware speci?ations motorola bus signal timing bus signal timing figure 13. external bus read timing (gpcm controlled?rlx = 0 or 1, acs = 10) figure 14. external bus read timing (gpcm controlled?rlx = 0 or 1, acs = 11) clkout a[0:31] cs x oe ts d[0:31], dp[0:3] b11 b12 b8 b22a b23 b26 b19 b18 b25 b24 clkout a[0:31] cs x oe ts d[0:31], dp[0:3] b11 b12 b22b b8 b22c b23 b24a b25 b26 b19 b18 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 29 bus signal timing figure 15. external bus read timing (gpcm controlled?rlx = 0 or 1, acs = 10, acs = 11) clkout a[0:31] cs x oe ts d[0:31], dp[0:3] b11 b12 b8 b22a b27 b27a b22b b22c b19 b18 b26 b23 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 30 mpc866/859 hardware speci?ations motorola bus signal timing bus signal timing figure 16 through figure 18 show the timing for the external bus write controlled by various gpcm factors. figure 16. external bus write timing (gpcm controlled?rlx = 0 or 1, csnt = 0) clkout a[0:31] cs x we [0:3] oe ts d[0:31], dp[0:3] b11 b8 b22 b23 b12 b30 b28 b25 b26 b8 b9 b29 b29b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 31 bus signal timing figure 17. external bus write timing (gpcm controlled?rlx = 0, csnt = 1) b23 b30a b30c clkout a[0:31] cs x oe we [0:3] ts d[0:31], dp[0:3] b11 b8 b22 b12 b28b b28d b25 b26 b8 b28a b9 b28c b29c b29g b29a b29f f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 32 mpc866/859 hardware speci?ations motorola bus signal timing bus signal timing figure 18. external bus write timing (gpcm controlled?rlx = 1, csnt = 1) b23 b22 b8 b12 b11 clkout a[0:31] cs x we [0:3] ts oe d[0:31], dp[0:3] b30d b30b b28b b28d b25 b29e b29i b26 b29d b29h b28a b28c b9 b8 b29b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 33 bus signal timing figure 19 shows the timing for the external bus controlled by the upm. figure 19. external bus timing (upm controlled signals) clkout cs x b31d b8 b31 b34 b32b gpl_a [0:5], gpl_b [0:5] bs_a [0:3], bs_b [0:3] a[0:31] b31c b31b b34a b32 b32a b32d b34b b36 b35b b35a b35 b33 b32c b33a b31a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 34 mpc866/859 hardware speci?ations motorola bus signal timing bus signal timing figure 20 shows the timing for the asynchronous asserted upwait signal controlled by the upm. figure 20. asynchronous upwait asserted detection in upm handled cycles timing figure 21 shows the timing for the asynchronous negated upwait signal controlled by the upm. figure 21. asynchronous upwait negated detection in upm handled cycles timing clkout cs x upwait gpl_a [0:5], gpl_b [0:5] bs_a [0:3], bs_b [0:3] b37 b38 clkout cs x upwait gpl_a [0:5], gpl_b [0:5] bs_a [0:3], bs_b [0:3] b37 b38 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 35 bus signal timing figure 22 shows the timing for the synchronous external master access controlled by the gpcm. figure 22. synchronous external master access timing (gpcm handled acs = 00) figure 23 shows the timing for the asynchronous external master memory access controlled by the gpcm. figure 23. asynchronous external master memory access timing (gpcm controlled?cs = 00) figure 24 shows the timing for the asynchronous external master control signals negation. figure 24. asynchronous external master?ontrol signals negation timing clkout ts a[0:31], tsiz[0:1], r/w , b urst cs x b41 b42 b40 b22 clkout as a[0:31], tsiz[0:1], r/w cs x b39 b40 b22 as cs x, we [0:3], oe , gplx , bs [0:3] b43 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 36 mpc866/859 hardware speci?ations motorola bus signal timing bus signal timing table 10 shows the interrupt timing for the mpc866/859. figure 25 shows the interrupt detection timing for the external level-sensitive lines. figure 25. interrupt detection timing for external level sensitive lines figure 26 shows the interrupt detection timing for the external edge-sensitive lines. figure 26. interrupt detection timing for external edge sensitive lines table 10. interrupt timing num characteristic 1 1 the timings i39 and i40 describe the testing conditions under which the irq lines are tested when being de?ed as level sensitive. the irq lines are synchronized internally and do not have to be asserted or negated with reference to the clkout. the timings i41, i42, and i43 are speci?d to allow the correct function of the irq lines detection circuitry, and has no direct relation with the total system interrupt latency that the mpc866/859 is able to support. all frequencies unit min max i39 irq x valid to clkout rising edge (setup time) 6.00 ns i40 irq x hold time after clkout 2.00 ns i41 irq x pulse width low 3.00 ns i42 irq x pulse width high 3.00 ns i43 irq x edge-to-edge time 4xt clockout clkout irq x i39 i40 clkout irq x i41 i42 i43 i43 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 37 bus signal timing table 11 shows the pcmcia timing for the mpc866/859. table 11. pcmcia timing num characteristic 33 mhz 40 mhz 50 mhz 66 mhz unit min max min max min max min max p44 a(0:31), reg valid to pcmcia strobe asserted 1 (min = 0.75 x b1 ?2.00) 1 psst = 1. otherwise, add psst times cycle time. psht = 0. otherwise, add psht times cycle time. these synchronous timings de?e when the w aitx signals are detected in order to freeze (or relieve) the pcmcia current cycle. the w aitx assertion will be effective only if it is detected 2 cycles before the psl timer expiration. see pcmcia interface in the mpc866 powerquicc user s manual . 20.70 16.70 13.00 9.40 ns p45 a(0:31), reg valid to ale negation 1 (min = 1.00 x b1 ?2.00) 28.30 23.00 18.00 13.20 ns p46 clkout to reg valid (max = 0.25 x b1 + 8.00) 7.60 15.60 6.30 14.30 5.00 13.00 3.80 11.80 ns p47 clkout to reg invalid (min = 0.25 x b1 + 1.00) 8.60 7.30 6.00 4.80 ns p48 clkout to ce1 , ce2 asserted (max = 0.25 x b1 + 8.00) 7.60 15.60 6.30 14.30 5.00 13.00 3.80 11.80 ns p49 clkout to ce1 , ce2 negated (max = 0.25 x b1 + 8.00) 7.60 15.60 6.30 14.30 5.00 13.00 3.80 11.80 ns p50 clkout to pcoe , iord , pcwe , io wr assert time (max = 0.00 x b1 + 11.00) 11.00 11.00 11.00 11.00 ns p51 clkout to pcoe , iord , pcwe , io wr negate time (max = 0.00 x b1 + 11.00) 2.00 11.00 2.00 11.00 2.00 11.00 2.00 11.00 ns p52 clkout to ale assert time (max = 0.25 x b1 + 6.30) 7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns p53 clkout to ale negate time (max = 0.25 x b1 + 8.00) 15.60 14.30 13.00 11.80 ns p54 pcwe , io wr negated to d(0:31) invalid 1 (min = 0.25 x b1 ?2.00) 5.60 4.30 3.00 1.80 ns p55 w ait a and w aitb valid to clkout rising edge 1 (min = 0.00 x b1 + 8.00) 8.00 8.00 8.00 8.00 ns p56 clkout rising edge to w ait a and w aitb invalid 1 (min = 0.00 x b1 + 2.00) 2.00 2.00 2.00 2.00 ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 38 mpc866/859 hardware speci?ations motorola bus signal timing bus signal timing figure 27 shows the pcmcia access cycle timing for the external bus read. figure 27. pcmcia access cycles timing external bus read clkout a[0:31] reg ce1 /ce2 pcoe , iord ts d[0:31] ale b19 b18 p53 p52 p52 p51 p50 p48 p49 p46 p45 p44 p47 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 39 bus signal timing figure 28 shows the pcmcia access cycle timing for the external bus write. figure 28. pcmcia access cycles timing external bus write figure 29 shows the pcmcia w ait signals detection timing. figure 29. pcmcia w ait signals detection timing clkout a[0:31] reg ce1 /ce2 pcwe , io wr ts d[0:31] ale b9 b8 p53 p52 p52 p51 p50 p48 p49 p46 p45 p44 p47 p54 clkout w ait x p55 p56 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 40 mpc866/859 hardware speci?ations motorola bus signal timing bus signal timing table 12 shows the pcmcia port timing for the mpc866/859. figure 30 shows the pcmcia output port timing for the mpc866/859. figure 30. pcmcia output port timing figure 31 shows the pcmcia output port timing for the mpc866/859. figure 31. pcmcia input port timing table 12. pcmcia port timing num characteristic 33 mhz 40 mhz 50 mhz 66 mhz unit min max min max min max min max p57 clkout to opx, valid (max = 0.00 x b1 + 19.00) 19.00 19.00 19.00 19.00 ns p58 hreset negated to opx drive 1 (min = 0.75 x b1 + 3.00) 1 op2 and op3 only. 25.70 21.70 18.00 14.40 ns p59 ip_xx valid to clkout rising edge (min = 0.00 x b1 + 5.00) 5.00 5.00 5.00 5.00 ns p60 clkout rising edge to ip_xx invalid (min = 0.00 x b1 + 1.00) 1.00 1.00 1.00 1.00 ns clkout hreset output signals op2, op3 p57 p58 clkout input signals p59 p60 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 41 bus signal timing table 13 shows the debug port timing for the mpc866/859. figure 32 shows the input timing for the debug port clock. figure 32. debug port clock input timing figure 33 shows the timing for the debug port. figure 33. debug port timings table 13. debug port timing num characteristic all frequencies unit min max d61 dsck cycle time 3xt clockout d62 dsck clock pulse width 1.25xt clockout d63 dsck rise and fall times 0.00 3.00 ns d64 dsdi input data setup time 8.00 ns d65 dsdi data hold time 5.00 ns d66 dsck low to dsdo data valid 0.00 15.00 ns d67 dsck low to dsdo invalid 0.00 2.00 ns dsck d61 d61 d63 d62 d62 d63 dsck dsdi dsdo d64 d65 d66 d67 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 42 mpc866/859 hardware speci?ations motorola bus signal timing bus signal timing table 14 shows the reset timing for the mpc866/859. table 14. reset timing num characteristic 33 mhz 40 mhz 50 mhz 66 mhz unit min max min max min max min max r69 clkout to hreset high impedance (max = 0.00 x b1 + 20.00) 20.00 20.00 20.00 20.00 ns r70 clkout to sreset high impedance (max = 0.00 x b1 + 20.00) 20.00 20.00 20.00 20.00 ns r71 rstconf pulse width (min = 17.00 x b1) 515.20 425.00 340.00 257.60 ns r72 r73 con?uration data to hreset rising edge setup time (min = 15.00 x b1 + 50.00) 504.50 425.00 350.00 277.30 ns r74 con?uration data to rstconf rising edge setup time (min = 0.00 x b1 + 350.00) 350.00 350.00 350.00 350.00 ns r75 con?uration data hold time after rstconf negation (min = 0.00 x b1 + 0.00) 0.00 0.00 0.00 0.00 ns r76 con?uration data hold time after hreset negation (min = 0.00 x b1 + 0.00) 0.00 0.00 0.00 0.00 ns r77 hreset and rstconf asserted to data out drive (max = 0.00 x b1 + 25.00) 25.00 25.00 25.00 25.00 ns r78 rstconf negated to data out high impedance (max = 0.00 x b1 + 25.00) 25.00 25.00 25.00 25.00 ns r79 clkout of last rising edge before chip three-states hreset to data out high impedance (max = 0.00 x b1 + 25.00) 25.00 25.00 25.00 25.00 ns r80 dsdi, dsck setup (min = 3.00 x b1) 90.90 75.00 60.00 45.50 ns r81 dsdi, dsck hold time (min = 0.00 x b1 + 0.00) 0.00 0.00 0.00 0.00 ns r82 sreset negated to clkout rising edge for dsdi and dsck sample (min = 8.00 x b1) 242.40 200.00 160.00 121.20 ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 43 bus signal timing figure 34 shows the reset timing for the data bus con?uration. figure 34. reset timing?on?uration from data bus figure 35 shows the reset timing for the data bus weak drive during con?uration. figure 35. reset timing?ata bus weak drive during con?uration hreset rstconf d[0:31] (in) r71 r74 r73 r75 r76 clkout hreset d[0:31] (out) (weak) rstconf r69 r79 r77 r78 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 44 mpc866/859 hardware speci?ations motorola ieee 1149.1 electrical specifications ieee 1149.1 electrical specifications figure 36 shows the reset timing for the debug port con?uration. figure 36. reset timing?ebug port con?uration 11 ieee 1149.1 electrical speci?ations table 15 shows the jtag timings for the mpc866/859 shown in figure 37 through figure 40. table 15. jtag timing num characteristic all frequencies unit min max j82 tck cycle time 100.00 ns j83 tck clock pulse width measured at 1.5 v 40.00 ns j84 tck rise and fall times 0.00 10.00 ns j85 tms, tdi data setup time 5.00 ns j86 tms, tdi data hold time 25.00 ns j87 tck low to tdo data valid 27.00 ns j88 tck low to tdo data invalid 0.00 ns j89 tck low to tdo high impedance 20.00 ns j90 trst assert time 100.00 ns j91 trst setup time to tck low 40.00 ns j92 tck falling edge to output valid 50.00 ns j93 tck falling edge to output valid out of high impedance 50.00 ns j94 tck falling edge to output high impedance 50.00 ns j95 boundary scan input valid to tck rising edge 50.00 ns j96 tck rising edge to boundary scan input invalid 50.00 ns clkout sreset dsck, dsdi r70 r82 r80 r80 r81 r81 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 45 ieee 1149.1 electrical specifications figure 37. jtag test clock input timing figure 38. jtag test access port timing diagram figure 39. jtag trst timing diagram tck j82 j83 j82 j83 j84 j84 tck tms, tdi tdo j85 j86 j87 j88 j89 tck trst j91 j90 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 46 mpc866/859 hardware speci?ations motorola cpm electrical characteristics cpm electrical characteristics figure 40. boundary scan (jtag) timing diagram 12 cpm electrical characteristics this section provides the ac and dc electrical speci?ations for the communications processor module (cpm) of the mpc866/859. 12.1 pip/pio ac electrical speci?ations table 16 shows the pip/pio ac timings as shown in figure 41 through figure 45. table 16. pip/pio timing num characteristic all frequencies unit min max 21 data-in setup time to stbi low 0 ns 22 data-in hold time to stbi high 2.5 ?t3 1 1 t3 = speci?ation 23 clk 23 stbi pulse width 1.5 clk 24 stbo pulse width 1 clk ?5ns ns 25 data-out setup time to stbo low 2 clk 26 data-out hold time from stbo high 5 clk 27 stbi low to stbo low (rx interlock) 2 clk 28 stbi low to stbo high (tx interlock) 2 clk 29 data-in setup time to clock high 15 ns 30 data-in hold time from clock high 7.5 ns 31 clock low to data-out valid (cpu writes data, control, or direction) 25 ns tck output signals output signals output signals j92 j94 j93 j95 j96 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 47 cpm electrical characteristics figure 41. pip rx (interlock mode) timing diagram figure 42. pip tx (interlock mode) timing diagram figure 43. pip rx (pulse mode) timing diagram data-in stbi 23 24 22 stbo 27 21 data-out 24 23 26 28 25 stbo (output) stbi (input) data-in 23 22 21 stbi (input) stbo (output) 24 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 48 mpc866/859 hardware speci?ations motorola cpm electrical characteristics cpm electrical characteristics figure 44. pip tx (pulse mode) timing diagram figure 45. parallel i/o data-in/data-out timing diagram 12.2 port c interrupt ac electrical speci?ations table 17 shows timings for port c interrupts. table 17. port c interrupt timing num characteristic 33.34 mhz unit min max 35 port c interrupt pulse width low (edge-triggered mode) 55 ns 36 port c interrupt minimum time between active edges 55 ns data-out 24 26 25 stbo (output) stbi (input) 23 clko data-in 29 31 30 data-out f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 49 cpm electrical characteristics figure 46 shows the port c interrupt detection timing. figure 46. port c interrupt detection timing 12.3 idma controller ac electrical speci?ations table 18 shows the idma controller timings as shown in figure 47 through figure 50. figure 47. idma external requests timing diagram table 18. idma controller timing num characteristic all frequencies unit min max 40 dreq setup time to clock high 7 ns 41 dreq hold time from clock high 3 ns 42 sd a ck assertion delay from clock high 12 ns 43 sd a ck negation delay from clock low 12 ns 44 sd a ck negation delay from t a low 20 ns 45 sd a ck negation delay from clock high 15 ns 46 t a assertion to falling edge of the clock setup time (applies to external t a )7 ns port c 35 36 (input) 41 40 dreq (input) clko (output) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 50 mpc866/859 hardware speci?ations motorola cpm electrical characteristics cpm electrical characteristics figure 48. sd a ck timing diagram?eripheral write, externally-generated t a figure 49. sd a ck timing diagram?eripheral write, internally-generated t a data 42 46 43 clko (output) ts (output) r/w (output) t a (input) sd a ck data 42 44 clko (output) ts (output) r/w (output) t a (output) sd a ck f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 51 cpm electrical characteristics figure 50. sd a ck timing diagram?eripheral read, internally-generated t a 12.4 baud rate generator ac electrical speci?ations table 19 shows the baud rate generator timings as shown in figure 51. figure 51. baud rate generator timing diagram table 19. baud rate generator timing num characteristic all frequencies unit min max 50 brgo rise and fall time 10 ns 51 brgo duty cycle 40 60 % 52 brgo cycle 40 ns data 42 45 clko (output) ts (output) r/w (output) t a (output) sd a ck 52 50 51 brgox 50 51 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 52 mpc866/859 hardware speci?ations motorola cpm electrical characteristics cpm electrical characteristics 12.5 timer ac electrical speci?ations table 20 shows the general-purpose timer timings as shown in figure 52. figure 52. cpm general-purpose timers timing diagram 12.6 serial interface ac electrical speci?ations table 21 shows the serial interface timings as shown in figure 53 through figure 57. table 20. timer timing num characteristic all frequencies unit min max 61 tin/tga te rise and fall time 10 ns 62 tin/tga te low time 1 clk 63 tin/tga te high time 2 clk 64 tin/tga te cycle time 3 clk 65 clko low to t out valid 3 25 ns table 21. si timing num characteristic all frequencies unit min max 70 l1rclk, l1tclk frequency (dsc = 0) 1, 2 syncclk/2.5 mhz 71 l1rclk, l1tclk width low (dsc = 0) 2 p + 10 ns 71a l1rclk, l1tclk width high (dsc = 0) 3 p + 10 ns 72 l1txd, l1st(1?), l1rq , l1clko rise/fall time ? 15.00 ns 73 l1rsync, l1tsync valid to l1clk edge (sync setup time) 20.00 ns 74 l1clk edge to l1rsync, l1tsync, invalid (sync hold time) 35.00 ns clko tin/tga te (input) t out (output) 64 65 61 62 63 61 60 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 53 cpm electrical characteristics 75 l1rsync, l1tsync rise/fall time 15.00 ns 76 l1rxd valid to l1clk edge (l1rxd setup time) 17.00 ns 77 l1clk edge to l1rxd invalid (l1rxd hold time) 13.00 ns 78 l1clk edge to l1st(1?) valid 4 10.00 45.00 ns 78a l1sync valid to l1st(1?) valid 10.00 45.00 ns 79 l1clk edge to l1st(1?) invalid 10.00 45.00 ns 80 l1clk edge to l1txd valid 10.00 55.00 ns 80a l1tsync valid to l1txd valid 4 10.00 55.00 ns 81 l1clk edge to l1txd high impedance 0.00 42.00 ns 82 l1rclk, l1tclk frequency (dsc =1) 16.00 or syncclk/2 mhz 83 l1rclk, l1tclk width low (dsc =1) p + 10 ns 83a l1rclk, l1tclk width high (dsc = 1) 3 p + 10 ns 84 l1clk edge to l1clko valid (dsc = 1) 30.00 ns 85 l1rq valid before falling edge of l1tsync 4 1.00 l1tclk 86 l1gr setup time 2 42.00 ns 87 l1gr hold time 42.00 ns 88 l1clk edge to l1sync valid (fsd = 00) cnt = 0000, byt = 0, dsc = 0) 0.00 ns 1 the ratio syncclk/l1rclk must be greater than 2.5/1. 2 these specs are valid for idl mode only. 3 where p = 1/clkout. thus, for a 25-mhz clko1 rate, p = 40 ns. 4 these strobes and txd on the ?st bit of the frame become valid after l1clk edge or l1sync, whichever is later. table 21. si timing (continued) num characteristic all frequencies unit min max f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 54 mpc866/859 hardware speci?ations motorola cpm electrical characteristics cpm electrical characteristics figure 53. si receive timing diagram with normal clocking (dsc = 0) l1rxd (input) l1rclk (fe=0, ce=0) (input) l1rclk (fe=1, ce=1) (input) l1rsync (input) l1st(4-1) (output) 71 72 70 71a rfsd=1 75 73 74 77 78 76 79 bit0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 55 cpm electrical characteristics figure 54. si receive timing with double-speed clocking (dsc = 1) l1rxd (input) l1rclk (fe=1, ce=1) (input) l1rclk (fe=0, ce=0) (input) l1rsync (input) l1st(4-1) (output) 72 rfsd=1 75 73 74 77 78 76 79 83a 82 l1clko (output) 84 bit0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 56 mpc866/859 hardware speci?ations motorola cpm electrical characteristics cpm electrical characteristics figure 55. si transmit timing diagram (dsc = 0) l1txd (output) l1tclk (fe=0, ce=0) (input) l1tclk (fe=1, ce=1) (input) l1tsync (input) l1st(4-1) (output) 71 70 72 73 75 74 80a 80 78 tfsd=0 81 79 bit0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 57 cpm electrical characteristics figure 56. si transmit timing with double speed clocking (dsc = 1) l1txd (output) l1rclk (fe=0, ce=0) (input) l1rclk (fe=1, ce=1) (input) l1rsync (input) l1st(4-1) (output) 72 tfsd=0 75 73 74 78a 80 79 83a 82 l1clko (output) 84 bit0 78 81 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 58 mpc866/859 hardware speci?ations motorola cpm electrical characteristics cpm electrical characteristics figure 57. idl timing b17 b16 b14 b13 b12 b11 b10 d1 a b27 b26 b25 b24 b23 b22 b21 b20 d2 m b15 l1rxd (input) l1txd (output) l1st(4-1) (output) l1rq (output) 73 77 123456789 10 11 12 13 14 15 16 17 18 19 20 74 80 b17 b16 b15 b14 b13 b12 b11 b10 d1 a b27 b26 b25 b24 b23 b22 b21 b20 d2 m 71 71 l1gr (input) 78 85 72 76 87 86 l1rsync (input) l1rclk (input) 81 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 59 cpm electrical characteristics 12.7 scc in nmsi mode electrical speci?ations table 22 shows the nmsi external clock timings. table 23 shows the nmsi internal clock timings. table 22. nmsi external clock timings num characteristic all frequencies unit min max 100 rclk1 and tclk1 width high 1 1 the ratios syncclk/rclk1 and syncclk/tclk1 must be greater than or equal to 2.25/1. 1/syncclk ns 101 rclk1 and tclk1 width low 1/syncclk +5 ns 102 rclk1 and tclk1 rise/fall time 15.00 ns 103 txd1 active delay (from tclk1 falling edge) 0.00 50.00 ns 104 r ts1 active/inactive delay (from tclk1 falling edge) 0.00 50.00 ns 105 cts1 setup time to tclk1 rising edge 5.00 ns 106 rxd1 setup time to rclk1 rising edge 5.00 ns 107 rxd1 hold time from rclk1 rising edge 2 2 also applies to cd and cts hold time when they are used as an external sync signal. 5.00 ns 108 cd1 setup time to rclk1 rising edge 5.00 ns table 23. nmsi internal clock timings num characteristic all frequencies unit min max 100 rclk1 and tclk1 frequency 1 1 the ratios syncclk/rclk1 and syncclk/tclk1 must be greater or equal to 3/1. 0.00 syncclk/3 mhz 102 rclk1 and tclk1 rise/fall time ns 103 txd1 active delay (from tclk1 falling edge) 0.00 30.00 ns 104 r ts1 active/inactive delay (from tclk1 falling edge) 0.00 30.00 ns 105 cts1 setup time to tclk1 rising edge 40.00 ns 106 rxd1 setup time to rclk1 rising edge 40.00 ns 107 rxd1 hold time from rclk1 rising edge 2 2 also applies to cd and cts hold time when they are used as an external sync signals. 0.00 ns 108 cd1 setup time to rclk1 rising edge 40.00 ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 60 mpc866/859 hardware speci?ations motorola cpm electrical characteristics cpm electrical characteristics figure 58 through figure 60 show the nmsi timings. figure 58. scc nmsi receive timing diagram figure 59. scc nmsi transmit timing diagram rclk1 cd1 (input) 102 100 107 108 107 rxd1 (input) cd1 (sync input) 102 101 106 tclk1 cts1 (input) 102 100 104 107 txd1 (output) cts1 (sync input) 102 101 r ts1 (output) 105 103 104 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 61 cpm electrical characteristics figure 60. hdlc bus timing diagram 12.8 ethernet electrical speci?ations table 24 shows the ethernet timings as shown in figure 61 through figure 65. table 24. ethernet timing num characteristic all frequencies unit min max 120 clsn width high 40 ns 121 rclk1 rise/fall time 15 ns 122 rclk1 width low 40 ns 123 rclk1 clock period 1 80 120 ns 124 rxd1 setup time 20 ns 125 rxd1 hold time 5 ns 126 rena active delay (from rclk1 rising edge of the last data bit) 10 ns 127 rena width low 100 ns 128 tclk1 rise/fall time 15 ns 129 tclk1 width low 40 ns 130 tclk1 clock period 1 99 101 ns 131 txd1 active delay (from tclk1 rising edge) 50 ns 132 txd1 inactive delay (from tclk1 rising edge) 6.5 50 ns 133 tena active delay (from tclk1 rising edge) 10 50 ns 134 tena inactive delay (from tclk1 rising edge) 10 50 ns tclk1 cts1 (echo input) 102 100 104 txd1 (output) 102 101 r ts1 (output) 103 104 107 105 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 62 mpc866/859 hardware speci?ations motorola cpm electrical characteristics cpm electrical characteristics figure 61. ethernet collision timing diagram figure 62. ethernet receive timing diagram 135 rstr t active delay (from tclk1 falling edge) 10 50 ns 136 rstr t inactive delay (from tclk1 falling edge) 10 50 ns 137 reject width low 1 clk 138 clko1 low to sd a ck asserted 2 ?0ns 139 clko1 low to sd a ck negated 2 ?0ns 1 the ratios syncclk/rclk1 and syncclk/tclk1 must be greater or equal to 2/1. 2 sd a ck is asserted whenever the sdma writes the incoming frame da into memory. table 24. ethernet timing (continued) num characteristic all frequencies unit min max clsn(cts1 ) 120 (input) rclk1 121 rxd1 (input) 121 rena(cd1 ) (input) 125 124 123 127 126 last bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 63 cpm electrical characteristics figure 63. ethernet transmit timing diagram figure 64. cam interface receive start timing diagram figure 65. cam interface reject timing diagram tclk1 128 txd1 (output) 128 tena(r ts1 ) (input) notes: transmit clock invert (tci) bit in gsmr is set. if rena is deasserted before tena, or rena is not asserted at all during transmit, then the csl bit is set in the buffer descriptor at the end of the frame transmission. 1. 2. rena(cd1 ) (input) 133 134 132 131 121 129 rclk1 rxd1 (input) rstr t (output) 0 136 125 1 1 bit1 bit2 start frame delimiter reject 137 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 64 mpc866/859 hardware speci?ations motorola cpm electrical characteristics cpm electrical characteristics 12.9 smc transparent ac electrical speci?ations table 25 shows the smc transparent timings as shown in figure 66. figure 66. smc transparent timing diagram table 25. smc transparent timing num characteristic all frequencies unit min max 150 smclk clock period 1 1 sync clk must be at least twice as fast as smclk. 100 ns 151 smclk width low 50 ns 151a smclk width high 50 ns 152 smclk rise/fall time 15 ns 153 smtxd active delay (from smclk falling edge) 10 50 ns 154 smrxd/smsync setup time 20 ns 155 rxd1/smsync hold time 5 ns smclk smrxd (input) 152 150 smtxd (output) 152 151 smsync 151a 154 153 155 154 155 note 1 note: this delay is equal to an integer number of character-length clocks. 1. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 65 cpm electrical characteristics 12.10 spi master ac electrical speci?ations table 26 shows the spi master timings as shown in figure 67 and figure 68. figure 67. spi master (cp = 0) timing diagram table 26. spi master timing num characteristic all frequencies unit min max 160 master cycle time 4 1024 t cyc 161 master clock (sck) high or low time 2 512 t cyc 162 master data setup time (inputs) 15 ns 163 master data hold time (inputs) 0 ns 164 master data valid (after sck edge) 10 ns 165 master data hold time (outputs) 0 ns 166 rise time output 15 ns 167 fall time output 15 ns spimosi (output) spiclk (ci=0) (output) spiclk (ci=1) (output) spimiso (input) 162 data 166 167 161 161 160 msb lsb msb msb data lsb msb 167 166 163 166 167 165 164 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 66 mpc866/859 hardware speci?ations motorola cpm electrical characteristics cpm electrical characteristics figure 68. spi master (cp = 1) timing diagram 12.11 spi slave ac electrical speci?ations table 27 shows the spi slave timings as shown in figure 69 and figure 70. table 27. spi slave timing num characteristic all frequencies unit min max 170 slave cycle time 2 t cyc 171 slave enable lead time 15 ns 172 slave enable lag time 15 ns 173 slave clock (spiclk) high or low time 1 t cyc 174 slave sequential transfer delay (does not require deselect) 1 t cyc 175 slave data setup time (inputs) 20 ns 176 slave data hold time (inputs) 20 ns 177 slave access time 50 ns spimosi (output) spiclk (ci=0) (output) spiclk (ci=1) (output) spimiso (input) data 166 167 161 161 160 msb lsb msb msb data lsb msb 167 166 163 166 167 165 164 162 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 67 cpm electrical characteristics figure 69. spi slave (cp = 0) timing diagram figure 70. spi slave (cp = 1) timing diagram spimosi (input) spiclk (ci=0) (input) spiclk (ci=1) (input) spimiso (output) 180 data 181 182 173 173 170 msb lsb msb 181 177 182 175 179 spisel (input) 171 172 174 data msb lsb msb undef 181 178 176 182 spimosi (input) spiclk (ci=0) (input) spiclk (ci=1) (input) spimiso (output) 180 data 181 182 msb lsb 181 177 182 175 179 spisel (input) 174 data msb lsb undef 178 176 182 msb msb 172 173 173 171 170 181 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 68 mpc866/859 hardware speci?ations motorola cpm electrical characteristics cpm electrical characteristics 12.12 i 2 c ac electrical speci?ations table 28 shows the i 2 c (scl < 100 khz) timings. table 28. i 2 c timing (scl < 100 khz) num characteristic all frequencies unit min max 200 scl clock frequency (slave) 0 100 khz 200 scl clock frequency (master) 1 1 scl frequency is given by scl = brgclk_frequency / ((brg register + 3) * pre_scaler * 2). the ratio syncclk/(brgclk/pre_scaler) must be greater or equal to 4/1. 1.5 100 khz 202 bus free time between transmissions 4.7 s 203 low period of scl 4.7 s 204 high period of scl 4.0 s 205 start condition setup time 4.7 s 206 start condition hold time 4.0 s 207 data hold time 0 s 208 data setup time 250 ns 209 sdl/scl rise time 1 s 210 sdl/scl fall time 300 ns 211 stop condition setup time 4.7 s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 69 cpm electrical characteristics table 29 shows the i 2 c (scl > 100 khz) timings. figure 71 shows the i 2 c bus timing. figure 71. i 2 c bus timing diagram table 29. i 2 c timing (scl > 100 khz) num characteristic expression all frequencies unit min max 200 scl clock frequency (slave) fscl 0 brgclk/48 hz 200 scl clock frequency (master) 1 1 scl frequency is given by scl = brgclk_frequency / ((brg register + 3) * pre_scaler * 2). the ratio syncclk/(brg_clk/pre_scaler) must be greater or equal to 4/1. fscl brgclk/16512 brgclk/48 hz 202 bus free time between transmissions 1/(2.2 * fscl) s 203 low period of scl 1/(2.2 * fscl) s 204 high period of scl 1/(2.2 * fscl) s 205 start condition setup time 1/(2.2 * fscl) s 206 start condition hold time 1/(2.2 * fscl) s 207 data hold time 0 s 208 data setup time 1/(40 * fscl) s 209 sdl/scl rise time 1/(10 * fscl) s 210 sdl/scl fall time 1/(33 * fscl) s 211 stop condition setup time 1/2(2.2 * fscl) s scl 202 205 203 207 204 208 206 209 211 210 sda f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 70 mpc866/859 hardware speci?ations motorola utopia ac electrical specifications utopia ac electrical specifications 13 utopia ac electrical speci?ations table 30 through table 32 show the ac electrical speci?ations for the utopia interface. table 30. utopia master (muxed mode) electrical speci?ations num signal characteristic direction min max unit u1 utpclk rise/fall time (internal clock option) output 4 ns duty cycle 50 50 % frequency 33 mhz u2 utpb, soc, rxenb , txenb , rxaddr, and txaddr-active delay (and phreq and phsel active delay in mphy mode) output 2 16 ns u3 utpb, soc, rxclav and txclav setup time input 4 ns u4 utpb, soc, rxclav and txclav hold time input 1 ns table 31. utopia master (split bus mode) electrical speci?ations num signal characteristic direction min max unit u1 utpclk rise/fall time (internal clock option) output 4 ns duty cycle 50 50 % frequency 33 mhz u2 utpb, soc, rxenb , txenb , rxaddr and txaddr active delay (phreq and phsel active delay in mphy mode) output 2 16 ns u3 utpb_aux, soc_aux, rxclav, and txclav setup time input 4 ns u4 utpb_aux, soc_aux, rxclav, and txclav hold time input 1 ns table 32. utopia slave (split bus mode) electrical speci?ations num signal characteristic direction min max unit u1 utpclk rise/fall time (external clock option) input 4 ns duty cycle 40 60 % frequency 33 mhz u2 utpb, soc, rxclav and txclav active delay output 2 16 ns u3 utpb_aux, soc_aux, rxenb , txenb , rxaddr, and txaddr setup time input 4 ns u4 utpb_aux, soc_aux, rxenb , txenb , rxaddr, and txaddr hold time input 1 ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 71 utopia ac electrical specifications figure 72 shows signal timings during utopia receive operations. figure 72. utopia receive timing figure 73 shows signal timings during utopia transmit operations. figure 73. utopia transmit timing utpclk utpb rxenb u1 3 2 soc 4 rxclav phreqn 3 4 highz at mphy highz at mph y u1 u2 u3 u4 u4 u3 u2 utpclk utpb txenb 1 2 soc 5 txclav phseln 3 4 5 highz at mphy high-z at mphy u1 u1 u2 u2 u2 u3 u4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 72 mpc866/859 hardware speci?ations motorola fec electrical characteristics fec electrical characteristics 14 fec electrical characteristics this section provides the ac electrical speci?ations for the fast ethernet controller (fec). note that the timing speci?ations for the mii signals are independent of system clock frequency (part speed designation). also, mii signals use ttl signal levels compatible with devices operating at either 5.0 or 3.3 v. 14.1 mii receive signal timing (mii_rxd [3:0], mii_rx_dv, mii_rx_er, mii_rx_clk) the receiver functions correctly up to a mii_rx_clk maximum frequency of 25 mhz + 1%. there is no minimum frequency requirement. in addition, the processor clock frequency must exceed the mii_rx_clk frequency ?1%. table 33 shows the timings for mii receive signal. figure 74 shows the timings for mii receive signal. figure 74. mii receive signal timing diagram 14.2 mii transmit signal timing (mii_txd[3:0], mii_tx_en, mii_tx_er, mii_tx_clk) the transmitter functions correctly up to a mii_tx_clk maximum frequency of 25 mhz +1%. there is no minimum frequency requirement. in addition, the processor clock frequency must exceed the mii_tx_clk frequency - 1%. table 33. mii receive signal timing num characteristic min max unit m1 mii_rxd[3:0], mii_rx_dv, mii_rx_er to mii_rx_clk setup 5 ns m2 mii_rx_clk to mii_rxd[3:0], mii_rx_dv, mii_rx_er hold 5 ns m3 mii_rx_clk pulse width high 35% 65% mii_rx_clk period m4 mii_rx_clk pulse width low 35% 65% mii_rx_clk period m1 m2 mii_rx_clk (input) mii_rxd[3:0] (inputs) mii_rx_dv mii_rx_er m3 m4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 73 fec electrical characteristics table 34 shows information on the mii transmit signal timing. figure 75 shows the mii transmit signal timing diagram. figure 75. mii transmit signal timing diagram 14.3 mii async inputs signal timing (mii_crs, mii_col) table 35 shows the timing for on the mii async inputs signal. figure 76 shows the mii asynchronous inputs signal timing diagram. figure 76. mii async inputs timing diagram table 34. mii transmit signal timing num characteristic min max unit m5 mii_tx_clk to mii_txd[3:0], mii_tx_en, mii_tx_er invalid 5 ns m6 mii_tx_clk to mii_txd[3:0], mii_tx_en, mii_tx_er valid ?5 m7 mii_tx_clk pulse width high 35% 65% mii_tx_clk period m8 mii_tx_clk pulse width low 35% 65% mii_tx_clk period table 35. mii async inputs signal timing num characteristic min max unit m9 mii_crs, mii_col minimum pulse width 1.5 mii_tx_clk period m6 mii_tx_clk (input) mii_txd[3:0] (outputs) mii_tx_en mii_tx_er m5 m7 m8 mii_crs, mii_col m9 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 74 mpc866/859 hardware speci?ations motorola fec electrical characteristics fec electrical characteristics 14.4 mii serial management channel timing (mii_mdio, mii_mdc) table 36 shows the timing for the mii serial management channel signal. the fec functions correctly with a maximum mdc frequency in excess of 2.5 mhz. the exact upper bound is under investigation. figure 77 shows the mii serial management channel timing diagram. figure 77. mii serial management channel timing diagram table 36. mii serial management channel timing num characteristic min max unit m10 mii_mdc falling edge to mii_mdio output invalid (minimum propagation delay) 0 ns m11 mii_mdc falling edge to mii_mdio output valid (maximum propagation delay) ?5 ns m12 mii_mdio (input) to mii_mdc rising edge setup 10 ns m13 mii_mdio (input) to mii_mdc rising edge hold 0 ns m14 mii_mdc pulse width high 40% 60% mii_mdc period m15 mii_mdc pulse width low 40% 60% mii_mdc period m11 mii_mdc (output) mii_mdio (output) m12 m13 mii_mdio (input) m10 m14 mm15 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 75 mechanical data and ordering information 15 mechanical data and ordering information table 37 shows information on the mpc866/859 derivative devices. table 38 identi?s the packages and operating frequencies orderable for the mpc866/859 derivative devices. table 37. mpc866/859 derivatives device number of sccs 1 1 serial communications controller (scc). ethernet support multi-channel hdlc support atm support cache size instruction data mpc866t 4 10/100 mbps yes yes 4 kbyte 4 kbytes mpc866p 4 10/100 mbps yes yes 16 kbyte 8 kbytes MPC859t 1 (scc1) 10/100 mbps yes yes 4 kbyte 4 kbytes MPC859dsl 1 (scc1) 10/100 mbps no up to 4 addresses 4 kbyte 4 kbytes table 38. mpc866/859 package/frequency orderable package type temperature (tj) frequency (mhz) order number plastic ball grid array (zp suf?) 0?to 95? 50 MPC859dslzp50 66 MPC859dslzp66 100 mpc866pzp100 mpc866tzp100 MPC859pzp100 MPC859tzp100 133 mpc866pzp133 mpc866tzp133 MPC859pzp133 MPC859tzp133 plastic ball grid array (czp suf?) ?0?to 100? tbd 1 1 additional extended temperature devices can be made available at 50, 66, 80, and100mhz. tbd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 76 mpc866/859 hardware speci?ations motorola mechanical data and ordering information mechanical data and ordering information 15.1 pin assignments figure 78 shows the top view pinout of the pbga package. for additional information, see the mpc866 powerquicc family user s manual . note: this is the top view of the device. figure 78. pinout of the pbga package pd3 irq7 d0 d4 d1 d2 d3 d5 vddl d6 d7 d29 clkout ipa3 dp2 a2 a7 a14 a27 a29 a30 a28 a31 vddl bsa2 we1 we3 ce2a cs1 cs4 a5 a11 18 16 141312111098765 32 4 17 15 1 19 a1 a6 a13 a17 a21 a23 a22 tsiz0 bsa3 m_crs we2 gpla2 ce1a wr cs5 a4 a10 gplb4 a0 pa15 a3 a12 a16 a20 a24 a26 tsiz1 bsa1 we0 gpla1 gpla3 cs0 t a cs7 pb31 a9 gpla4 pb30 pc14 pc15 n/c n/c a15 a19 a25 a18 bsa0 gpla0 n/c cs6 gpla5 bdip cs2 pa14 a8 tea pb28 pc13 pb29 vddh vddh bi bg cs3 pa13 bb pb27 pc12 vddl gnd gnd ts irq3 vddl pa12 b urst pb26 tms pa11 irq6 ipb4 br tdo ipb3 trst m_mdio tck irq2 ipb0 m_col tdi ipb7 vddl pb24 pb25 ipb1 ipb2 ipb5 pa10 aleb pc11 pa9 pb21 gnd ipb6 alea baddr30 pb23 irq4 pc10 pc9 pb20 as op1 op0 pa 8 modck1 pb22 pc8 pc7 baddr28 baddr29 modck2 pa 6 vddl pa 7 pa5 pb16 texp extclk hreset pb18 extal pb19 pb17 vddl gnd r s t c o n f s r e s e t vddl pa3 gnd xtal pa 4 pa2 pd12 vddh w a i t _a p o r e s e t w a i t _b pb15 vddh vddl pc6 pc5 pd11 vddh d12 d17 d9 d15 d22 d25 d31 ipa6 ipa0 ipa7 n/c ipa1 pc4 pd7 vddsyn pa 1 pb14 pd4 irq1 d8 d23 d11 d16 d19 d21 d26 d30 ipa5 ipa2 n/c ipa4 pd15 pd5 vsssyn pa 0 pd13 pd6 irq0 d13 d27 d10 d14 d18 d20 d24 d28 dp1 dp0 n/c dp3 pd9 m_tx_en vsssyn1 pd14 b a c d e f g h j k l m n p r t u v w pd10 pd8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 77 mechanical data and ordering information table 39 contains a list of the mpc866 input and output signals and shows multiplexing and pin assignments. table 39. pin assignments name pin number type a[0:31] b19, b18, a18, c16, b17, a17, b16, a16, d15, c15, b15, a15, c14, b14, a14, d12, c13, b13, d9, d11, c12, b12, b10, b11, c11, d10, c10, a13, a10, a12, a11, a9 bidirectional three-state tsiz0 reg b9 bidirectional three-state tsiz1 c9 bidirectional three-state rd/wr b2 bidirectional three-state b urst f1 bidirectional three-state bdip gpl_b5 d2 output ts f3 bidirectional active pull-up t a c2 bidirectional active pull-up tea d1 open-drain bi e3 bidirectional active pull-up irq2 rsv h3 bidirectional three-state irq4 kr retr y spkrout k1 bidirectional three-state cr irq3 f2 input d[0:31] w14, w12, w11, w10, w13, w9, w7, w6, u13, t11, v11, u11, t13, v13, v10, t10, u10, t12, v9, u9, v8, u8, t9, u12, v7, t8, u7, v12, v6, w5, u6, t7 bidirectional three-state dp0 irq3 v3 bidirectional three-state dp1 irq4 v5 bidirectional three-state dp2 irq5 w4 bidirectional three-state dp3 irq6 v4 bidirectional three-state br g4 bidirectional f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 78 mpc866/859 hardware speci?ations motorola mechanical data and ordering information mechanical data and ordering information bg e2 bidirectional bb e1 bidirectional active pull-up frz irq6 g3 bidirectional irq0 v14 input irq1 u14 input m_tx_clk irq7 w15 input cs [0:5] c3, a2, d4, e4, a4, b4 output cs6 ce1_b d5 output cs7 ce2_b c4 output we0 bs_b0 iord c7 output we1 bs_b1 io wr a6 output we2 bs_b2 pcoe b6 output we3 bs_b3 pcwe a5 output bs_a [0:3] d8, c8, a7, b8 output gpl_a0 gpl_b0 d7 output oe gpl_a1 gpl_b1 c6 output gpl_a [2:3] gpl_b [2:3] cs [2?] b5, c5 output upwaita gpl_a4 c1 bidirectional upwaitb gpl_b4 b1 bidirectional gpl_a5 d3 output poreset r2 input table 39. pin assignments (continued) name pin number type f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 79 mechanical data and ordering information rstconf p3 input hreset n4 open-drain sreset p2 open-drain xtal p1 analog output extal n1 analog input (3.3v only) clkout w3 output extclk n2 input (3.3v only) texp n3 output ale_a mii-txd1 k2 output ce1_a mii-txd2 b3 output ce2_a mii-txd3 a3 output w ait_a soc_split 2 r3 input w ait_b r4 input ip_a0 utpb_split0 2 mii-rxd3 t5 input ip_a1 utpb_split1 2 mii-rxd2 t4 input ip_a2 iois16_a utpb_split2 2 mii-rxd1 u3 input ip_a3 utpb_split3 2 mii-rxd0 w2 input ip_a4 utpb_split4 2 mii-rxclk u4 input ip_a5 utpb_split5 2 mii-rxerr u5 input ip_a6 utpb_split6 2 mii-txerr t6 input ip_a7 utpb_split7 2 mii-rxdv t3 input table 39. pin assignments (continued) name pin number type f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 80 mpc866/859 hardware speci?ations motorola mechanical data and ordering information mechanical data and ordering information ale_b dsck/at1 j1 bidirectional three-state ip_b[0:1] iwp[0:1] vfls[0:1] h2, j3 bidirectional ip_b2 iois16_b at 2 j2 bidirectional three-state ip_b3 iwp2 vf2 g1 bidirectional ip_b4 lwp0 vf0 g2 bidirectional ip_b5 lwp1 vf1 j4 bidirectional ip_b6 dsdi at 0 k3 bidirectional three-state ip_b7 ptr at 3 h1 bidirectional three-state op0 mii-txd0 utpclk_split 2 l4 bidirectional op1 l2 output op2 modck1 sts l1 bidirectional op3 modck2 dsdo m4 bidirectional baddr30 reg k4 output baddr[28:29] m3, m2 output as l3 input pa15 rxd1 rxd4 c18 bidirectional pa14 txd1 txd4 d17 bidirectional (optional: open-drain) table 39. pin assignments (continued) name pin number type f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 81 mechanical data and ordering information pa13 rxd2 e17 bidirectional pa12 txd2 f17 bidirectional (optional: open-drain) pa11 l1txdb rxd3 g16 bidirectional (optional: open-drain) pa10 l1rxdb txd3 j17 bidirectional (optional: open-drain) pa 9 l1txda rxd4 k18 bidirectional (optional: open-drain) pa 8 l1rxda txd4 l17 bidirectional (optional: open-drain) pa 7 clk1 l1rclka brgo1 tin1 m19 bidirectional pa 6 clk2 t out1 m17 bidirectional pa 5 clk3 l1tclka brgo2 tin2 n18 bidirectional pa 4 clk4 t out2 p19 bidirectional pa 3 clk5 brgo3 tin3 p17 bidirectional pa 2 clk6 t out3 l1rclkb r18 bidirectional pa 1 clk7 brgo4 tin4 t19 bidirectional table 39. pin assignments (continued) name pin number type f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 82 mpc866/859 hardware speci?ations motorola mechanical data and ordering information mechanical data and ordering information pa 0 clk8 t out4 l1tclkb u19 bidirectional pb31 spisel reject1 c17 bidirectional (optional: open-drain) pb30 spiclk rstr t2 c19 bidirectional (optional: open-drain) pb29 spimosi e16 bidirectional (optional: open-drain) pb28 spimiso brgo4 d19 bidirectional (optional: open-drain) pb27 i2csda brgo1 e19 bidirectional (optional: open-drain) pb26 i2cscl brgo2 f19 bidirectional (optional: open-drain) pb25 rxaddr3 2 smtxd1 j16 bidirectional (optional: open-drain) pb24 txaddr3 2 smrxd1 j18 bidirectional (optional: open-drain) pb23 txaddr2 2 sd a ck1 smsyn1 k17 bidirectional (optional: open-drain) pb22 txaddr4 2 sd a ck2 smsyn2 l19 bidirectional (optional: open-drain) pb21 smtxd2 l1clkob phsel1 1 txaddr1 2 k16 bidirectional (optional: open-drain) pb20 smrxd2 l1clkoa phsel0 1 txaddr0 2 l16 bidirectional (optional: open-drain) table 39. pin assignments (continued) name pin number type f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 83 mechanical data and ordering information pb19 r ts1 l1st1 n19 bidirectional (optional: open-drain) pb18 rxaddr4 2 r ts2 l1st2 n17 bidirectional (optional: open-drain) pb17 l1rqb l1st3 r ts3 phreq1 1 rxaddr1 2 p18 bidirectional (optional: open-drain) pb16 l1rqa l1st4 r ts4 phreq0 1 rxaddr0 2 n16 bidirectional (optional: open-drain) pb15 brgo3 txclav rxclav r17 bidirectional pb14 rxaddr2 2 rstr t1 u18 bidirectional pc15 dreq0 r ts1 l1st1 rxclav txclav d16 bidirectional pc14 dreq1 r ts2 l1st2 d18 bidirectional pc13 l1rqb l1st3 rts3 e18 bidirectional pc12 l1rqa l1st4 rts4 f18 bidirectional pc11 cts1 j19 bidirectional table 39. pin assignments (continued) name pin number type f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 84 mpc866/859 hardware speci?ations motorola mechanical data and ordering information mechanical data and ordering information pc10 cd1 tga te1 k19 bidirectional pc9 cts2 l18 bidirectional pc8 cd2 tga te2 m18 bidirectional pc7 cts3 l1tsyncb sd a ck2 m16 bidirectional pc6 cd3 l1rsyncb r19 bidirectional pc5 cts4 l1tsynca sdack1 t18 bidirectional pc4 cd4 l1rsynca t17 bidirectional pd15 l1tsynca mii-rxd3 utpb0 u17 bidirectional pd14 l1rsynca mii-rxd2 utpb1 v19 bidirectional pd13 l1tsyncb mii-rxd1 utpb2 v18 bidirectional pd12 l1rsyncb mii-mdc utpb3 r16 bidirectional pd11 rxd3 mii-txerr rxenb t16 bidirectional pd10 txd3 mii-rxd0 txenb w18 bidirectional table 39. pin assignments (continued) name pin number type f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 85 mechanical data and ordering information pd9 rxd4 mii-txd0 utpclk v17 bidirectional pd8 txd4 mii-mdc mii-rxclk w17 bidirectional pd7 r ts3 mii-rxerr utpb4 t15 bidirectional pd6 r ts4 mii-rxdv utpb5 v16 bidirectional pd5 reject2 mii-txd3 utpb6 u15 bidirectional pd4 reject3 mii-txd2 utpb7 u16 bidirectional pd3 reject4 mii-txd1 soc w16 bidirectional tms g18 input tdi dsdi h17 input tck dsck h16 input trst g19 input tdo dsdo g17 output mii_crs b7 input mii_mdio h18 bidirectional mii_txen v15 output mii_col h4 input vsssyn1 v1 pll analog vdd and gnd vsssyn u1 power table 39. pin assignments (continued) name pin number type f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 86 mpc866/859 hardware speci?ations motorola mechanical data and ordering information mechanical data and ordering information 15.2 mechanical dimensions of the pbga package for more information on the printed-circuit board layout of the pbga package, including thermal via design and suggested pad layout, please refer to plastic ball grid array application note (order number: an1231/d) available from your local motorola sales of?e. figure 79 shows the mechanical dimensions of the pbga package. vddsyn t1 power gnd f6, f7, f8, f9, f10, f11, f12, f13, f14, g6, g7, g8, g9, g10, g11, g12, g13, g14, h6, h7, h8, h9, h10, h11, h12, h13, h14, j6, j7, j8, j9, j10, j11, j12, j13, j14, k6, k7, k8, k9, k10, k11, k12, k13, k14, l6, l7, l8, l9, l10, l11, l12, l13, l14, m6, m7, m8, m9, m10, m11, m12, m13, m14, n6, n7, n8, n9, n10, n11, n12, n13, n14, p6, p7, p8, p9, p10, p11, p12, p13, p14 power vddl a8, m1, w8, h19, f4, f16, p4, p16, r1 power vddh e5, e6, e7, e8, e9, e10, e11, e12, e13, e14, e15, f5, f15, g5, g15, h5, h15, j5, j15, k5, k15, l5, l15, m5, m15, n5, n15, p5, p15, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, t14 power n/c d6, d13, d14, u2, v2, t2 no-connect 1 classic sar mode only 2 esar mode only table 39. pin assignments (continued) name pin number type f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 87 mechanical data and ordering information figure 79. mechanical dimensions and bottom surface nomenclature of the pbga package note: solder sphere composition for mpc866xzp, MPC859pzp, MPC859dslzp, and MPC859tzp is 62%sn 36%pb 2%ag f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 88 mpc866/859 hardware speci?ations motorola document revision history document revision history 16 document revision history table 40 lists signi?ant changes between revisions of this document. table 40. document revision history revision number date substantive changes 0 5/2002 initial revision 1 11/2002 added the 5-v tolerant pins, new package dimensions, and other changes. 1.1 4/2003 added the spec. b1d and changed spec. b1a. added the note solder sphere composition for mpc866xzp, MPC859dslzp, and MPC859tzp is 62%sn 36%pb 2%ag to figure 15-79. 1.2 4/2003 added the MPC859p. 1.3 5/2003 changed the spi master timing specs. 162 and 164. 1.4 7-8/2003 added txclav and rxclav to pb15 and pc15. changed b28a through b28d and b29b to show that trlx can be 0 or 1. added nontechnical reformatting. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 89 document revision history this page intentionally left blank f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 90 mpc866/859 hardware speci?ations motorola document revision history document revision history this page intentionally left blank f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mpc866/859 hardware speci?ations 91 document revision history this page intentionally left blank f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mpc866ec/d how to reach us: usa/europe/locations not listed: motorola literature distribution p.o. box 5405, denver, colorado 80217 1-480-768-2130 (800) 521-6274 japan: motorola japan ltd. sps, technical information center 3-20-1, minami-azabu minato-ku tokyo 106-8573 japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd. silicon harbour centre, 2 dai king street tai po industrial estate, tai po, n.t., hong kong 852-26668334 technical information center: (800) 521-6274 home page: www.motorola.com/semiconductors information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and speci?ally disclaims any and all liability, including without limitation consequential or incidental damages. ?ypical parameters which may be provided in motorola data sheets and/or speci?ations can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?ypicals must be validated for each customer application by customer s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its of?ers, employees, subsidiaries, af?iates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered in the u.s. patent and trademark of?e. digital dna is a trademark of motorola, inc. the described product contains a powerpc processor core. the powerpc name is a trademark of ibm corp. and used under license. all other product or service names are the property of their respective owners. motorola, inc. is an equal opportunity/af?mative action employer. ?motorola, inc. 2003 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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